379c373e99de9a8116298a25e17d95f5087a816b
3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
, Repl
, Cat
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from nmutil
.singlepipe
import ControlBase
25 from soc
.simple
.core_data
import FetchOutput
, FetchInput
27 from nmigen
.lib
.coding
import PriorityEncoder
29 from openpower
.decoder
.power_decoder
import create_pdecode
30 from openpower
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
31 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
32 from openpower
.decoder
.decode2execute1
import Data
33 from openpower
.decoder
.power_enums
import (MicrOp
, SVP64PredInt
, SVP64PredCR
,
35 from openpower
.state
import CoreState
36 from openpower
.consts
import (CR
, SVP64CROffs
, MSR
)
37 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
38 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
39 from soc
.simple
.core
import NonProductionCore
40 from soc
.config
.test
.test_loadstore
import TestMemPspec
41 from soc
.config
.ifetch
import ConfigFetchUnit
42 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
43 from soc
.debug
.jtag
import JTAG
44 from soc
.config
.pinouts
import get_pinspecs
45 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
46 from soc
.bus
.simple_gpio
import SimpleGPIO
47 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
48 from soc
.clock
.select
import ClockSelect
49 from soc
.clock
.dummypll
import DummyPLL
50 from openpower
.sv
.svstate
import SVSTATERec
51 from soc
.experiment
.icache
import ICache
53 from nmutil
.util
import rising_edge
56 def get_insn(f_instr_o
, pc
):
57 if f_instr_o
.width
== 32:
60 # 64-bit: bit 2 of pc decides which word to select
61 return f_instr_o
.word_select(pc
[2], 32)
63 # gets state input or reads from state regfile
66 def state_get(m
, res
, core_rst
, state_i
, name
, regfile
, regnum
):
69 # read the {insert state variable here}
70 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
72 sync
+= res_ok_delay
.eq(~state_i
.ok
)
73 with m
.If(state_i
.ok
):
74 # incoming override (start from pc_i)
75 comb
+= res
.eq(state_i
.data
)
77 # otherwise read StateRegs regfile for {insert state here}...
78 comb
+= regfile
.ren
.eq(1 << regnum
)
79 # ... but on a 1-clock delay
80 with m
.If(res_ok_delay
):
81 comb
+= res
.eq(regfile
.o_data
)
84 def get_predint(m
, mask
, name
):
85 """decode SVP64 predicate integer mask field to reg number and invert
86 this is identical to the equivalent function in ISACaller except that
87 it doesn't read the INT directly, it just decodes "what needs to be done"
88 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
90 * all1s is set to indicate that no mask is to be applied.
91 * regread indicates the GPR register number to be read
92 * invert is set to indicate that the register value is to be inverted
93 * unary indicates that the contents of the register is to be shifted 1<<r3
96 regread
= Signal(5, name
=name
+"regread")
97 invert
= Signal(name
=name
+"invert")
98 unary
= Signal(name
=name
+"unary")
99 all1s
= Signal(name
=name
+"all1s")
101 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
102 comb
+= all1s
.eq(1) # use 0b1111 (all ones)
103 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
104 comb
+= regread
.eq(3)
105 comb
+= unary
.eq(1) # 1<<r3 - shift r3 (single bit)
106 with m
.Case(SVP64PredInt
.R3
.value
):
107 comb
+= regread
.eq(3)
108 with m
.Case(SVP64PredInt
.R3_N
.value
):
109 comb
+= regread
.eq(3)
111 with m
.Case(SVP64PredInt
.R10
.value
):
112 comb
+= regread
.eq(10)
113 with m
.Case(SVP64PredInt
.R10_N
.value
):
114 comb
+= regread
.eq(10)
116 with m
.Case(SVP64PredInt
.R30
.value
):
117 comb
+= regread
.eq(30)
118 with m
.Case(SVP64PredInt
.R30_N
.value
):
119 comb
+= regread
.eq(30)
121 return regread
, invert
, unary
, all1s
124 def get_predcr(m
, mask
, name
):
125 """decode SVP64 predicate CR to reg number field and invert status
126 this is identical to _get_predcr in ISACaller
129 idx
= Signal(2, name
=name
+"idx")
130 invert
= Signal(name
=name
+"crinvert")
132 with m
.Case(SVP64PredCR
.LT
.value
):
133 comb
+= idx
.eq(CR
.LT
)
135 with m
.Case(SVP64PredCR
.GE
.value
):
136 comb
+= idx
.eq(CR
.LT
)
138 with m
.Case(SVP64PredCR
.GT
.value
):
139 comb
+= idx
.eq(CR
.GT
)
141 with m
.Case(SVP64PredCR
.LE
.value
):
142 comb
+= idx
.eq(CR
.GT
)
144 with m
.Case(SVP64PredCR
.EQ
.value
):
145 comb
+= idx
.eq(CR
.EQ
)
147 with m
.Case(SVP64PredCR
.NE
.value
):
148 comb
+= idx
.eq(CR
.EQ
)
150 with m
.Case(SVP64PredCR
.SO
.value
):
151 comb
+= idx
.eq(CR
.SO
)
153 with m
.Case(SVP64PredCR
.NS
.value
):
154 comb
+= idx
.eq(CR
.SO
)
159 class TestIssuerBase(Elaboratable
):
160 """TestIssuerBase - common base class for Issuers
162 takes care of power-on reset, peripherals, debug, DEC/TB,
163 and gets PC/MSR/SVSTATE from the State Regfile etc.
166 def __init__(self
, pspec
):
168 # test if microwatt compatibility is to be enabled
169 self
.microwatt_compat
= (hasattr(pspec
, "microwatt_compat") and
170 (pspec
.microwatt_compat
== True))
171 self
.alt_reset
= Signal(reset_less
=True) # not connected yet (microwatt)
173 # test is SVP64 is to be enabled
174 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
176 # and if regfiles are reduced
177 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
178 (pspec
.regreduce
== True))
180 # and if overlap requested
181 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
182 (pspec
.allow_overlap
== True))
184 # and get the core domain
185 self
.core_domain
= "coresync"
186 if (hasattr(pspec
, "core_domain") and
187 isinstance(pspec
.core_domain
, str)):
188 self
.core_domain
= pspec
.core_domain
190 # JTAG interface. add this right at the start because if it's
191 # added it *modifies* the pspec, by adding enable/disable signals
192 # for parts of the rest of the core
193 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
194 #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
195 self
.dbg_domain
= "dbgsync" # domain for DMI/JTAG clock
197 # XXX MUST keep this up-to-date with litex, and
198 # soc-cocotb-sim, and err.. all needs sorting out, argh
201 'eint', 'gpio', 'mspi0',
202 # 'mspi1', - disabled for now
203 # 'pwm', 'sd0', - disabled for now
205 self
.jtag
= JTAG(get_pinspecs(subset
=subset
),
206 domain
=self
.dbg_domain
)
207 # add signals to pspec to enable/disable icache and dcache
208 # (or data and intstruction wishbone if icache/dcache not included)
209 # https://bugs.libre-soc.org/show_bug.cgi?id=520
210 # TODO: do we actually care if these are not domain-synchronised?
211 # honestly probably not.
212 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
213 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
214 self
.wb_sram_en
= self
.jtag
.wb_sram_en
216 self
.wb_sram_en
= Const(1)
218 # add 4k sram blocks?
219 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
220 pspec
.sram4x4kblock
== True)
224 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
228 # add interrupt controller?
229 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
231 self
.xics_icp
= XICS_ICP()
232 self
.xics_ics
= XICS_ICS()
233 self
.int_level_i
= self
.xics_ics
.int_level_i
235 self
.ext_irq
= Signal()
237 # add GPIO peripheral?
238 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
240 self
.simple_gpio
= SimpleGPIO()
241 self
.gpio_o
= self
.simple_gpio
.gpio_o
243 # main instruction core. suitable for prototyping / demo only
244 self
.core
= core
= NonProductionCore(pspec
)
245 self
.core_rst
= ResetSignal(self
.core_domain
)
247 # instruction decoder. goes into Trap Record
248 #pdecode = create_pdecode()
249 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
250 self
.pdecode2
= PowerDecode2(None, state
=self
.cur_state
,
251 opkls
=IssuerDecode2ToOperand
,
252 svp64_en
=self
.svp64_en
,
253 regreduce_en
=self
.regreduce_en
)
254 pdecode
= self
.pdecode2
.dec
257 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
259 self
.update_svstate
= Signal() # set this if updating svstate
260 self
.new_svstate
= new_svstate
= SVSTATERec("new_svstate")
262 # Test Instruction memory
263 if hasattr(core
, "icache"):
264 # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
265 # truly dreadful. needs a huge reorg.
266 pspec
.icache
= core
.icache
267 self
.imem
= ConfigFetchUnit(pspec
).fu
270 self
.dbg
= CoreDebug()
271 self
.dbg_rst_i
= Signal(reset_less
=True)
273 # instruction go/monitor
274 self
.pc_o
= Signal(64, reset_less
=True)
275 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
276 self
.msr_i
= Data(64, "msr_i") # set "ok" to indicate "please change me"
277 self
.svstate_i
= Data(64, "svstate_i") # ditto
278 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
279 self
.busy_o
= Signal(reset_less
=True)
280 self
.memerr_o
= Signal(reset_less
=True)
282 # STATE regfile read /write ports for PC, MSR, SVSTATE
283 staterf
= self
.core
.regs
.rf
['state']
284 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
285 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
286 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
288 self
.state_w_msr
= staterf
.w_ports
['d_wr2'] # MSR wr
289 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
290 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
292 # DMI interface access
293 intrf
= self
.core
.regs
.rf
['int']
294 fastrf
= self
.core
.regs
.rf
['fast']
295 crrf
= self
.core
.regs
.rf
['cr']
296 xerrf
= self
.core
.regs
.rf
['xer']
297 self
.int_r
= intrf
.r_ports
['dmi'] # INT DMI read
298 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR DMI read
299 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER DMI read
300 self
.fast_r
= fastrf
.r_ports
['dmi'] # FAST DMI read
304 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
305 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
307 # hack method of keeping an eye on whether branch/trap set the PC
308 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
309 self
.state_nia
.wen
.name
= 'state_nia_wen'
310 # and whether SPR pipeline sets DEC or TB
311 self
.state_spr
= self
.core
.regs
.rf
['state'].w_ports
['state1']
313 # pulse to synchronize the simulator at instruction end
314 self
.insn_done
= Signal()
316 # indicate any instruction still outstanding, in execution
317 self
.any_busy
= Signal()
320 # store copies of predicate masks
321 self
.srcmask
= Signal(64)
322 self
.dstmask
= Signal(64)
324 # sigh, the wishbone addresses are not wishbone-compliant in microwatt
325 if self
.microwatt_compat
:
326 self
.ibus_adr
= Signal(32, name
='wishbone_insn_out.adr')
327 self
.dbus_adr
= Signal(32, name
='wishbone_data_out.adr')
329 # add an output of the PC and instruction, and whether it was requested
330 # this is for verilator debug purposes
331 if self
.microwatt_compat
:
332 self
.nia
= Signal(64)
333 self
.msr_o
= Signal(64)
334 self
.nia_req
= Signal(1)
335 self
.insn
= Signal(32)
336 self
.ldst_req
= Signal(1)
337 self
.ldst_addr
= Signal(1)
339 # for pausing dec/tb during an SPR pipeline event, this
340 # ensures that an SPR write (mtspr) to TB or DEC does not
341 # get overwritten by the DEC/TB FSM
342 self
.pause_dec_tb
= Signal()
344 def setup_peripherals(self
, m
):
345 comb
, sync
= m
.d
.comb
, m
.d
.sync
347 # okaaaay so the debug module must be in coresync clock domain
348 # but NOT its reset signal. to cope with this, set every single
349 # submodule explicitly in coresync domain, debug and JTAG
350 # in their own one but using *external* reset.
351 csd
= DomainRenamer(self
.core_domain
)
352 dbd
= DomainRenamer(self
.dbg_domain
)
354 if self
.microwatt_compat
:
355 m
.submodules
.core
= core
= self
.core
357 m
.submodules
.core
= core
= csd(self
.core
)
359 # this _so_ needs sorting out. ICache is added down inside
360 # LoadStore1 and is already a submodule of LoadStore1
361 if not isinstance(self
.imem
, ICache
):
362 m
.submodules
.imem
= imem
= csd(self
.imem
)
364 # set up JTAG Debug Module (in correct domain)
365 m
.submodules
.dbg
= dbg
= dbd(self
.dbg
)
367 m
.submodules
.jtag
= jtag
= dbd(self
.jtag
)
368 # TODO: UART2GDB mux, here, from external pin
369 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
370 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
372 # fixup the clocks in microwatt-compat mode (but leave resets alone
373 # so that microwatt soc.vhdl can pull a reset on the core or DMI
374 # can do it, just like in TestIssuer)
375 if self
.microwatt_compat
:
376 intclk
= ClockSignal(self
.core_domain
)
377 dbgclk
= ClockSignal(self
.dbg_domain
)
378 if self
.core_domain
!= 'sync':
379 comb
+= intclk
.eq(ClockSignal())
380 if self
.dbg_domain
!= 'sync':
381 comb
+= dbgclk
.eq(ClockSignal())
383 # drop the first 3 bits of the incoming wishbone addresses
384 # this can go if using later versions of microwatt (not now)
385 if self
.microwatt_compat
:
386 ibus
= self
.imem
.ibus
387 dbus
= self
.core
.l0
.cmpi
.wb_bus()
388 comb
+= self
.ibus_adr
.eq(Cat(Const(0, 3), ibus
.adr
))
389 comb
+= self
.dbus_adr
.eq(Cat(Const(0, 3), dbus
.adr
))
390 # microwatt verilator debug purposes
391 pi
= self
.core
.l0
.cmpi
.pi
.pi
392 comb
+= self
.ldst_req
.eq(pi
.addr_ok_o
)
393 comb
+= self
.ldst_addr
.eq(pi
.addr
)
395 cur_state
= self
.cur_state
397 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
399 for i
, sram
in enumerate(self
.sram4k
):
400 m
.submodules
["sram4k_%d" % i
] = csd(sram
)
401 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
403 # XICS interrupt handler
405 m
.submodules
.xics_icp
= icp
= csd(self
.xics_icp
)
406 m
.submodules
.xics_ics
= ics
= csd(self
.xics_ics
)
407 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
408 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
410 sync
+= cur_state
.eint
.eq(self
.ext_irq
) # connect externally
412 # GPIO test peripheral
414 m
.submodules
.simple_gpio
= simple_gpio
= csd(self
.simple_gpio
)
416 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
417 # XXX causes litex ECP5 test to get wrong idea about input and output
418 # (but works with verilator sim *sigh*)
419 # if self.gpio and self.xics:
420 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
422 # instruction decoder
423 pdecode
= create_pdecode()
424 m
.submodules
.dec2
= pdecode2
= csd(self
.pdecode2
)
426 m
.submodules
.svp64
= svp64
= csd(self
.svp64
)
428 # clock delay power-on reset
429 cd_por
= ClockDomain(reset_less
=True)
430 cd_sync
= ClockDomain()
431 m
.domains
+= cd_por
, cd_sync
432 core_sync
= ClockDomain(self
.core_domain
)
433 if self
.core_domain
!= "sync":
434 m
.domains
+= core_sync
435 if self
.dbg_domain
!= "sync":
436 dbg_sync
= ClockDomain(self
.dbg_domain
)
437 m
.domains
+= dbg_sync
439 ti_rst
= Signal(reset_less
=True)
440 delay
= Signal(range(4), reset
=3)
441 with m
.If(delay
!= 0):
442 m
.d
.por
+= delay
.eq(delay
- 1)
443 comb
+= cd_por
.clk
.eq(ClockSignal())
445 # power-on reset delay
446 core_rst
= ResetSignal(self
.core_domain
)
447 if self
.core_domain
!= "sync":
448 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
449 comb
+= core_rst
.eq(ti_rst
)
451 with m
.If(delay
!= 0 | dbg
.core_rst_o
):
452 comb
+= core_rst
.eq(1)
454 # connect external reset signal to DMI Reset
455 if self
.dbg_domain
!= "sync":
456 dbg_rst
= ResetSignal(self
.dbg_domain
)
457 comb
+= dbg_rst
.eq(self
.dbg_rst_i
)
459 # busy/halted signals from core
460 core_busy_o
= ~core
.p
.o_ready | core
.n
.o_data
.busy_o
# core is busy
461 comb
+= self
.busy_o
.eq(core_busy_o
)
462 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
464 # temporary hack: says "go" immediately for both address gen and ST
465 # XXX: st.go_i is set to 1 cycle delay to reduce combinatorial chains
467 ldst
= core
.fus
.fus
['ldst0']
468 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
469 # link addr-go direct to rel
470 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
)
471 m
.d
.sync
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
473 def do_dmi(self
, m
, dbg
):
474 """deals with DMI debug requests
476 currently only provides read requests for the INT regfile, CR and XER
477 it will later also deal with *writing* to these regfiles.
481 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
483 intrf
= self
.core
.regs
.rf
['int']
484 fastrf
= self
.core
.regs
.rf
['fast']
486 with m
.If(d_reg
.req
): # request for regfile access being made
487 # TODO: error-check this
488 # XXX should this be combinatorial? sync better?
490 comb
+= self
.int_r
.ren
.eq(1 << d_reg
.addr
)
492 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
493 comb
+= self
.int_r
.ren
.eq(1)
494 d_reg_delay
= Signal()
495 sync
+= d_reg_delay
.eq(d_reg
.req
)
496 with m
.If(d_reg_delay
):
497 # data arrives one clock later
498 comb
+= d_reg
.data
.eq(self
.int_r
.o_data
)
499 comb
+= d_reg
.ack
.eq(1)
502 with m
.If(d_fast
.req
): # request for regfile access being made
504 comb
+= self
.fast_r
.ren
.eq(1 << d_fast
.addr
)
506 comb
+= self
.fast_r
.addr
.eq(d_fast
.addr
)
507 comb
+= self
.fast_r
.ren
.eq(1)
508 d_fast_delay
= Signal()
509 sync
+= d_fast_delay
.eq(d_fast
.req
)
510 with m
.If(d_fast_delay
):
511 # data arrives one clock later
512 comb
+= d_fast
.data
.eq(self
.fast_r
.o_data
)
513 comb
+= d_fast
.ack
.eq(1)
515 # sigh same thing for CR debug
516 with m
.If(d_cr
.req
): # request for regfile access being made
517 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
518 d_cr_delay
= Signal()
519 sync
+= d_cr_delay
.eq(d_cr
.req
)
520 with m
.If(d_cr_delay
):
521 # data arrives one clock later
522 comb
+= d_cr
.data
.eq(self
.cr_r
.o_data
)
523 comb
+= d_cr
.ack
.eq(1)
526 with m
.If(d_xer
.req
): # request for regfile access being made
527 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
528 d_xer_delay
= Signal()
529 sync
+= d_xer_delay
.eq(d_xer
.req
)
530 with m
.If(d_xer_delay
):
531 # data arrives one clock later
532 comb
+= d_xer
.data
.eq(self
.xer_r
.o_data
)
533 comb
+= d_xer
.ack
.eq(1)
535 def tb_dec_fsm(self
, m
, spr_dec
):
538 this is a FSM for updating either dec or tb. it runs alternately
539 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
540 value to DEC, however the regfile has "passthrough" on it so this
543 see v3.0B p1097-1099 for Timer Resource and p1065 and p1076
546 comb
, sync
= m
.d
.comb
, m
.d
.sync
547 state_rf
= self
.core
.regs
.rf
['state']
548 state_r_dectb
= state_rf
.r_ports
['issue'] # DEC/TB
549 state_w_dectb
= state_rf
.w_ports
['issue'] # DEC/TB
553 # initiates read of current DEC
554 with m
.State("DEC_READ"):
555 comb
+= state_r_dectb
.ren
.eq(1<<StateRegs
.DEC
)
556 with m
.If(~self
.pause_dec_tb
):
559 # waits for DEC read to arrive (1 cycle), updates with new value
560 # respects if dec/tb writing has been paused
561 with m
.State("DEC_WRITE"):
562 with m
.If(self
.pause_dec_tb
):
563 # if paused, return to reading
567 # TODO: MSR.LPCR 32-bit decrement mode
568 comb
+= new_dec
.eq(state_r_dectb
.o_data
- 1)
569 comb
+= state_w_dectb
.wen
.eq(1<<StateRegs
.DEC
)
570 comb
+= state_w_dectb
.i_data
.eq(new_dec
)
571 # copy to cur_state for decoder, for an interrupt
572 sync
+= spr_dec
.eq(new_dec
)
575 # initiates read of current TB
576 with m
.State("TB_READ"):
577 comb
+= state_r_dectb
.ren
.eq(1<<StateRegs
.TB
)
578 with m
.If(~self
.pause_dec_tb
):
581 # waits for read TB to arrive, initiates write of current TB
582 # respects if dec/tb writing has been paused
583 with m
.State("TB_WRITE"):
584 with m
.If(self
.pause_dec_tb
):
585 # if paused, return to reading
589 comb
+= new_tb
.eq(state_r_dectb
.o_data
+ 1)
590 comb
+= state_w_dectb
.wen
.eq(1<<StateRegs
.TB
)
591 comb
+= state_w_dectb
.i_data
.eq(new_tb
)
596 def elaborate(self
, platform
):
599 comb
, sync
= m
.d
.comb
, m
.d
.sync
600 cur_state
= self
.cur_state
601 pdecode2
= self
.pdecode2
604 # set up peripherals and core
605 core_rst
= self
.core_rst
606 self
.setup_peripherals(m
)
608 # reset current state if core reset requested
610 m
.d
.sync
+= self
.cur_state
.eq(0)
612 # check halted condition: requested PC to execute matches DMI stop addr
613 # and immediately stop. address of 0xffff_ffff_ffff_ffff can never
616 comb
+= halted
.eq(dbg
.stop_addr_o
== dbg
.state
.pc
)
618 comb
+= dbg
.core_stopped_i
.eq(1)
619 comb
+= dbg
.terminate_i
.eq(1)
621 # PC and instruction from I-Memory
622 comb
+= self
.pc_o
.eq(cur_state
.pc
)
623 self
.pc_changed
= Signal() # note write to PC
624 self
.msr_changed
= Signal() # note write to MSR
625 self
.sv_changed
= Signal() # note write to SVSTATE
627 # read state either from incoming override or from regfile
628 state
= CoreState("get") # current state (MSR/PC/SVSTATE)
629 state_get(m
, state
.msr
, core_rst
, self
.msr_i
,
631 self
.state_r_msr
, StateRegs
.MSR
)
632 state_get(m
, state
.pc
, core_rst
, self
.pc_i
,
634 self
.state_r_pc
, StateRegs
.PC
)
635 state_get(m
, state
.svstate
, core_rst
, self
.svstate_i
,
636 "svstate", # read SVSTATE
637 self
.state_r_sv
, StateRegs
.SVSTATE
)
639 # don't write pc every cycle
640 comb
+= self
.state_w_pc
.wen
.eq(0)
641 comb
+= self
.state_w_pc
.i_data
.eq(0)
643 # connect up debug state. note "combinatorially same" below,
644 # this is a bit naff, passing state over in the dbg class, but
645 # because it is combinatorial it achieves the desired goal
646 comb
+= dbg
.state
.eq(state
)
648 # this bit doesn't have to be in the FSM: connect up to read
649 # regfiles on demand from DMI
652 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
653 # (which uses that in PowerDecoder2 to raise 0x900 exception)
654 self
.tb_dec_fsm(m
, cur_state
.dec
)
656 # while stopped, allow updating the MSR, PC and SVSTATE.
657 # these are mainly for debugging purposes (including DMI/JTAG)
658 with m
.If(dbg
.core_stopped_i
):
659 with m
.If(self
.pc_i
.ok
):
660 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
661 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
662 sync
+= self
.pc_changed
.eq(1)
663 with m
.If(self
.msr_i
.ok
):
664 comb
+= self
.state_w_msr
.wen
.eq(1 << StateRegs
.MSR
)
665 comb
+= self
.state_w_msr
.i_data
.eq(self
.msr_i
.data
)
666 sync
+= self
.msr_changed
.eq(1)
667 with m
.If(self
.svstate_i
.ok | self
.update_svstate
):
668 with m
.If(self
.svstate_i
.ok
): # over-ride from external source
669 comb
+= self
.new_svstate
.eq(self
.svstate_i
.data
)
670 comb
+= self
.state_w_sv
.wen
.eq(1 << StateRegs
.SVSTATE
)
671 comb
+= self
.state_w_sv
.i_data
.eq(self
.new_svstate
)
672 sync
+= self
.sv_changed
.eq(1)
674 # start renaming some of the ports to match microwatt
675 if self
.microwatt_compat
:
676 self
.core
.o
.core_terminate_o
.name
= "terminated_out"
677 # names of DMI interface
678 self
.dbg
.dmi
.addr_i
.name
= 'dmi_addr'
679 self
.dbg
.dmi
.din
.name
= 'dmi_din'
680 self
.dbg
.dmi
.dout
.name
= 'dmi_dout'
681 self
.dbg
.dmi
.req_i
.name
= 'dmi_req'
682 self
.dbg
.dmi
.we_i
.name
= 'dmi_wr'
683 self
.dbg
.dmi
.ack_o
.name
= 'dmi_ack'
684 # wishbone instruction bus
685 ibus
= self
.imem
.ibus
686 ibus
.adr
.name
= 'wishbone_insn_out.adr'
687 ibus
.dat_w
.name
= 'wishbone_insn_out.dat'
688 ibus
.sel
.name
= 'wishbone_insn_out.sel'
689 ibus
.cyc
.name
= 'wishbone_insn_out.cyc'
690 ibus
.stb
.name
= 'wishbone_insn_out.stb'
691 ibus
.we
.name
= 'wishbone_insn_out.we'
692 ibus
.dat_r
.name
= 'wishbone_insn_in.dat'
693 ibus
.ack
.name
= 'wishbone_insn_in.ack'
694 ibus
.stall
.name
= 'wishbone_insn_in.stall'
696 dbus
= self
.core
.l0
.cmpi
.wb_bus()
697 dbus
.adr
.name
= 'wishbone_data_out.adr'
698 dbus
.dat_w
.name
= 'wishbone_data_out.dat'
699 dbus
.sel
.name
= 'wishbone_data_out.sel'
700 dbus
.cyc
.name
= 'wishbone_data_out.cyc'
701 dbus
.stb
.name
= 'wishbone_data_out.stb'
702 dbus
.we
.name
= 'wishbone_data_out.we'
703 dbus
.dat_r
.name
= 'wishbone_data_in.dat'
704 dbus
.ack
.name
= 'wishbone_data_in.ack'
705 dbus
.stall
.name
= 'wishbone_data_in.stall'
710 yield from self
.pc_i
.ports()
711 yield from self
.msr_i
.ports()
714 yield from self
.core
.ports()
715 yield from self
.imem
.ports()
716 yield self
.core_bigendian_i
722 def external_ports(self
):
723 if self
.microwatt_compat
:
724 ports
= [self
.core
.o
.core_terminate_o
,
726 self
.alt_reset
, # not connected yet
727 self
.nia
, self
.insn
, self
.nia_req
, self
.msr_o
,
728 self
.ldst_req
, self
.ldst_addr
,
732 ports
+= list(self
.dbg
.dmi
.ports())
733 # for dbus/ibus microwatt, exclude err btw and cti
734 for name
, sig
in self
.imem
.ibus
.fields
.items():
735 if name
not in ['err', 'bte', 'cti', 'adr']:
737 for name
, sig
in self
.core
.l0
.cmpi
.wb_bus().fields
.items():
738 if name
not in ['err', 'bte', 'cti', 'adr']:
740 # microwatt non-compliant with wishbone
741 ports
.append(self
.ibus_adr
)
742 ports
.append(self
.dbus_adr
)
745 ports
= self
.pc_i
.ports()
746 ports
= self
.msr_i
.ports()
747 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
751 ports
+= list(self
.jtag
.external_ports())
753 # don't add DMI if JTAG is enabled
754 ports
+= list(self
.dbg
.dmi
.ports())
756 ports
+= list(self
.imem
.ibus
.fields
.values())
757 ports
+= list(self
.core
.l0
.cmpi
.wb_bus().fields
.values())
760 for sram
in self
.sram4k
:
761 ports
+= list(sram
.bus
.fields
.values())
764 ports
+= list(self
.xics_icp
.bus
.fields
.values())
765 ports
+= list(self
.xics_ics
.bus
.fields
.values())
766 ports
.append(self
.int_level_i
)
768 ports
.append(self
.ext_irq
)
771 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
772 ports
.append(self
.gpio_o
)
780 class TestIssuerInternal(TestIssuerBase
):
781 """TestIssuer - reads instructions from TestMemory and issues them
783 efficiency and speed is not the main goal here: functional correctness
784 and code clarity is. optimisations (which almost 100% interfere with
785 easy understanding) come later.
788 def fetch_fsm(self
, m
, dbg
, core
, pc
, msr
, svstate
, nia
, is_svp64_mode
,
789 fetch_pc_o_ready
, fetch_pc_i_valid
,
790 fetch_insn_o_valid
, fetch_insn_i_ready
):
793 this FSM performs fetch of raw instruction data, partial-decodes
794 it 32-bit at a time to detect SVP64 prefixes, and will optionally
795 read a 2nd 32-bit quantity if that occurs.
799 pdecode2
= self
.pdecode2
800 cur_state
= self
.cur_state
801 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
803 # also note instruction fetch failed
804 if hasattr(core
, "icache"):
805 fetch_failed
= core
.icache
.i_out
.fetch_failed
808 fetch_failed
= Const(0, 1)
811 # set priv / virt mode on I-Cache, sigh
812 if isinstance(self
.imem
, ICache
):
813 comb
+= self
.imem
.i_in
.priv_mode
.eq(~msr
[MSR
.PR
])
814 comb
+= self
.imem
.i_in
.virt_mode
.eq(msr
[MSR
.IR
]) # Instr. Redir (VM)
816 with m
.FSM(name
='fetch_fsm'):
819 with m
.State("IDLE"):
820 # fetch allowed if not failed and stopped but not stepping
821 # (see dmi.py for how core_stop_o is generated)
822 with m
.If(~fetch_failed
& ~dbg
.core_stop_o
):
823 comb
+= fetch_pc_o_ready
.eq(1)
824 with m
.If(fetch_pc_i_valid
& ~pdecode2
.instr_fault
826 # instruction allowed to go: start by reading the PC
827 # capture the PC and also drop it into Insn Memory
828 # we have joined a pair of combinatorial memory
829 # lookups together. this is Generally Bad.
830 comb
+= self
.imem
.a_pc_i
.eq(pc
)
831 comb
+= self
.imem
.a_i_valid
.eq(1)
832 comb
+= self
.imem
.f_i_valid
.eq(1)
833 # transfer state to output
834 sync
+= cur_state
.pc
.eq(pc
)
835 sync
+= cur_state
.svstate
.eq(svstate
) # and svstate
836 sync
+= cur_state
.msr
.eq(msr
) # and msr
838 m
.next
= "INSN_READ" # move to "wait for bus" phase
840 # dummy pause to find out why simulation is not keeping up
841 with m
.State("INSN_READ"):
842 # when using "single-step" mode, checking dbg.stopping_o
843 # prevents progress. allow fetch to proceed once started
845 #if self.allow_overlap:
846 # stopping = dbg.stopping_o
848 # stopping: jump back to idle
851 with m
.If(self
.imem
.f_busy_o
&
852 ~pdecode2
.instr_fault
): # zzz...
853 # busy but not fetch failed: stay in wait-read
854 comb
+= self
.imem
.a_pc_i
.eq(pc
)
855 comb
+= self
.imem
.a_i_valid
.eq(1)
856 comb
+= self
.imem
.f_i_valid
.eq(1)
858 # not busy (or fetch failed!): instruction fetched
859 # when fetch failed, the instruction gets ignored
861 if hasattr(core
, "icache"):
862 # blech, icache returns actual instruction
863 insn
= self
.imem
.f_instr_o
865 # but these return raw memory
866 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
869 # decode the SVP64 prefix, if any
870 comb
+= svp64
.raw_opcode_in
.eq(insn
)
871 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
872 # pass the decoded prefix (if any) to PowerDecoder2
873 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
874 sync
+= pdecode2
.is_svp64_mode
.eq(is_svp64_mode
)
875 # remember whether this is a prefixed instruction,
876 # so the FSM can readily loop when VL==0
877 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
878 # calculate the address of the following instruction
879 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
880 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
881 with m
.If(~svp64
.is_svp64_mode
):
882 # with no prefix, store the instruction
883 # and hand it directly to the next FSM
884 sync
+= dec_opcode_i
.eq(insn
)
885 m
.next
= "INSN_READY"
887 # fetch the rest of the instruction from memory
888 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
889 comb
+= self
.imem
.a_i_valid
.eq(1)
890 comb
+= self
.imem
.f_i_valid
.eq(1)
891 m
.next
= "INSN_READ2"
893 # not SVP64 - 32-bit only
894 sync
+= nia
.eq(cur_state
.pc
+ 4)
895 sync
+= dec_opcode_i
.eq(insn
)
896 if self
.microwatt_compat
:
897 # for verilator debug purposes
898 comb
+= self
.insn
.eq(insn
)
899 comb
+= self
.nia
.eq(cur_state
.pc
)
900 comb
+= self
.msr_o
.eq(cur_state
.msr
)
901 comb
+= self
.nia_req
.eq(1)
902 m
.next
= "INSN_READY"
904 with m
.State("INSN_READ2"):
905 with m
.If(self
.imem
.f_busy_o
): # zzz...
906 # busy: stay in wait-read
907 comb
+= self
.imem
.a_i_valid
.eq(1)
908 comb
+= self
.imem
.f_i_valid
.eq(1)
910 # not busy: instruction fetched
911 if hasattr(core
, "icache"):
912 # blech, icache returns actual instruction
913 insn
= self
.imem
.f_instr_o
915 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
916 sync
+= dec_opcode_i
.eq(insn
)
917 m
.next
= "INSN_READY"
918 # TODO: probably can start looking at pdecode2.rm_dec
919 # here or maybe even in INSN_READ state, if svp64_mode
920 # detected, in order to trigger - and wait for - the
923 pmode
= pdecode2
.rm_dec
.predmode
925 if pmode != SVP64PredMode.ALWAYS.value:
926 fire predicate loading FSM and wait before
929 sync += self.srcmask.eq(-1) # set to all 1s
930 sync += self.dstmask.eq(-1) # set to all 1s
931 m.next = "INSN_READY"
934 with m
.State("INSN_READY"):
935 # hand over the instruction, to be decoded
936 comb
+= fetch_insn_o_valid
.eq(1)
937 with m
.If(fetch_insn_i_ready
):
941 def fetch_predicate_fsm(self
, m
,
942 pred_insn_i_valid
, pred_insn_o_ready
,
943 pred_mask_o_valid
, pred_mask_i_ready
):
944 """fetch_predicate_fsm - obtains (constructs in the case of CR)
945 src/dest predicate masks
947 https://bugs.libre-soc.org/show_bug.cgi?id=617
948 the predicates can be read here, by using IntRegs r_ports['pred']
949 or CRRegs r_ports['pred']. in the case of CRs it will have to
950 be done through multiple reads, extracting one relevant at a time.
951 later, a faster way would be to use the 32-bit-wide CR port but
952 this is more complex decoding, here. equivalent code used in
953 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
955 note: this ENTIRE FSM is not to be called when svp64 is disabled
959 pdecode2
= self
.pdecode2
960 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
961 predmode
= rm_dec
.predmode
962 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
963 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
964 # get src/dst step, so we can skip already used mask bits
965 cur_state
= self
.cur_state
966 srcstep
= cur_state
.svstate
.srcstep
967 dststep
= cur_state
.svstate
.dststep
968 cur_vl
= cur_state
.svstate
.vl
971 sregread
, sinvert
, sunary
, sall1s
= get_predint(m
, srcpred
, 's')
972 dregread
, dinvert
, dunary
, dall1s
= get_predint(m
, dstpred
, 'd')
973 sidx
, scrinvert
= get_predcr(m
, srcpred
, 's')
974 didx
, dcrinvert
= get_predcr(m
, dstpred
, 'd')
976 # store fetched masks, for either intpred or crpred
977 # when src/dst step is not zero, the skipped mask bits need to be
978 # shifted-out, before actually storing them in src/dest mask
979 new_srcmask
= Signal(64, reset_less
=True)
980 new_dstmask
= Signal(64, reset_less
=True)
982 with m
.FSM(name
="fetch_predicate"):
984 with m
.State("FETCH_PRED_IDLE"):
985 comb
+= pred_insn_o_ready
.eq(1)
986 with m
.If(pred_insn_i_valid
):
987 with m
.If(predmode
== SVP64PredMode
.INT
):
988 # skip fetching destination mask register, when zero
990 sync
+= new_dstmask
.eq(-1)
991 # directly go to fetch source mask register
992 # guaranteed not to be zero (otherwise predmode
993 # would be SVP64PredMode.ALWAYS, not INT)
994 comb
+= int_pred
.addr
.eq(sregread
)
995 comb
+= int_pred
.ren
.eq(1)
996 m
.next
= "INT_SRC_READ"
997 # fetch destination predicate register
999 comb
+= int_pred
.addr
.eq(dregread
)
1000 comb
+= int_pred
.ren
.eq(1)
1001 m
.next
= "INT_DST_READ"
1002 with m
.Elif(predmode
== SVP64PredMode
.CR
):
1003 # go fetch masks from the CR register file
1004 sync
+= new_srcmask
.eq(0)
1005 sync
+= new_dstmask
.eq(0)
1008 sync
+= self
.srcmask
.eq(-1)
1009 sync
+= self
.dstmask
.eq(-1)
1010 m
.next
= "FETCH_PRED_DONE"
1012 with m
.State("INT_DST_READ"):
1013 # store destination mask
1014 inv
= Repl(dinvert
, 64)
1016 # set selected mask bit for 1<<r3 mode
1017 dst_shift
= Signal(range(64))
1018 comb
+= dst_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1019 sync
+= new_dstmask
.eq(1 << dst_shift
)
1021 # invert mask if requested
1022 sync
+= new_dstmask
.eq(self
.int_pred
.o_data ^ inv
)
1023 # skip fetching source mask register, when zero
1025 sync
+= new_srcmask
.eq(-1)
1026 m
.next
= "FETCH_PRED_SHIFT_MASK"
1027 # fetch source predicate register
1029 comb
+= int_pred
.addr
.eq(sregread
)
1030 comb
+= int_pred
.ren
.eq(1)
1031 m
.next
= "INT_SRC_READ"
1033 with m
.State("INT_SRC_READ"):
1035 inv
= Repl(sinvert
, 64)
1037 # set selected mask bit for 1<<r3 mode
1038 src_shift
= Signal(range(64))
1039 comb
+= src_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1040 sync
+= new_srcmask
.eq(1 << src_shift
)
1042 # invert mask if requested
1043 sync
+= new_srcmask
.eq(self
.int_pred
.o_data ^ inv
)
1044 m
.next
= "FETCH_PRED_SHIFT_MASK"
1046 # fetch masks from the CR register file
1047 # implements the following loop:
1048 # idx, inv = get_predcr(mask)
1050 # for cr_idx in range(vl):
1051 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle
1053 # mask |= 1 << cr_idx
1055 with m
.State("CR_READ"):
1056 # CR index to be read, which will be ready by the next cycle
1057 cr_idx
= Signal
.like(cur_vl
, reset_less
=True)
1058 # submit the read operation to the regfile
1059 with m
.If(cr_idx
!= cur_vl
):
1060 # the CR read port is unary ...
1062 # ... in MSB0 convention ...
1063 # ren = 1 << (7 - cr_idx)
1064 # ... and with an offset:
1065 # ren = 1 << (7 - off - cr_idx)
1066 idx
= SVP64CROffs
.CRPred
+ cr_idx
1067 comb
+= cr_pred
.ren
.eq(1 << (7 - idx
))
1068 # signal data valid in the next cycle
1069 cr_read
= Signal(reset_less
=True)
1070 sync
+= cr_read
.eq(1)
1071 # load the next index
1072 sync
+= cr_idx
.eq(cr_idx
+ 1)
1075 sync
+= cr_read
.eq(0)
1076 sync
+= cr_idx
.eq(0)
1077 m
.next
= "FETCH_PRED_SHIFT_MASK"
1079 # compensate for the one cycle delay on the regfile
1080 cur_cr_idx
= Signal
.like(cur_vl
)
1081 comb
+= cur_cr_idx
.eq(cr_idx
- 1)
1082 # read the CR field, select the appropriate bit
1083 cr_field
= Signal(4)
1086 comb
+= cr_field
.eq(cr_pred
.o_data
)
1087 comb
+= scr_bit
.eq(cr_field
.bit_select(sidx
, 1)
1089 comb
+= dcr_bit
.eq(cr_field
.bit_select(didx
, 1)
1091 # set the corresponding mask bit
1092 bit_to_set
= Signal
.like(self
.srcmask
)
1093 comb
+= bit_to_set
.eq(1 << cur_cr_idx
)
1095 sync
+= new_srcmask
.eq(new_srcmask | bit_to_set
)
1097 sync
+= new_dstmask
.eq(new_dstmask | bit_to_set
)
1099 with m
.State("FETCH_PRED_SHIFT_MASK"):
1100 # shift-out skipped mask bits
1101 sync
+= self
.srcmask
.eq(new_srcmask
>> srcstep
)
1102 sync
+= self
.dstmask
.eq(new_dstmask
>> dststep
)
1103 m
.next
= "FETCH_PRED_DONE"
1105 with m
.State("FETCH_PRED_DONE"):
1106 comb
+= pred_mask_o_valid
.eq(1)
1107 with m
.If(pred_mask_i_ready
):
1108 m
.next
= "FETCH_PRED_IDLE"
1110 def issue_fsm(self
, m
, core
, nia
,
1111 dbg
, core_rst
, is_svp64_mode
,
1112 fetch_pc_o_ready
, fetch_pc_i_valid
,
1113 fetch_insn_o_valid
, fetch_insn_i_ready
,
1114 pred_insn_i_valid
, pred_insn_o_ready
,
1115 pred_mask_o_valid
, pred_mask_i_ready
,
1116 exec_insn_i_valid
, exec_insn_o_ready
,
1117 exec_pc_o_valid
, exec_pc_i_ready
):
1120 decode / issue FSM. this interacts with the "fetch" FSM
1121 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
1122 (outgoing). also interacts with the "execute" FSM
1123 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
1125 SVP64 RM prefixes have already been set up by the
1126 "fetch" phase, so execute is fairly straightforward.
1131 pdecode2
= self
.pdecode2
1132 cur_state
= self
.cur_state
1133 new_svstate
= self
.new_svstate
1136 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
1138 # for updating svstate (things like srcstep etc.)
1139 comb
+= new_svstate
.eq(cur_state
.svstate
)
1141 # precalculate srcstep+1 and dststep+1
1142 cur_srcstep
= cur_state
.svstate
.srcstep
1143 cur_dststep
= cur_state
.svstate
.dststep
1144 next_srcstep
= Signal
.like(cur_srcstep
)
1145 next_dststep
= Signal
.like(cur_dststep
)
1146 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
1147 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
1149 # note if an exception happened. in a pipelined or OoO design
1150 # this needs to be accompanied by "shadowing" (or stalling)
1151 exc_happened
= self
.core
.o
.exc_happened
1152 # also note instruction fetch failed
1153 if hasattr(core
, "icache"):
1154 fetch_failed
= core
.icache
.i_out
.fetch_failed
1156 # set to fault in decoder
1157 # update (highest priority) instruction fault
1158 rising_fetch_failed
= rising_edge(m
, fetch_failed
)
1159 with m
.If(rising_fetch_failed
):
1160 sync
+= pdecode2
.instr_fault
.eq(1)
1162 fetch_failed
= Const(0, 1)
1163 flush_needed
= False
1165 with m
.FSM(name
="issue_fsm"):
1167 # sync with the "fetch" phase which is reading the instruction
1168 # at this point, there is no instruction running, that
1169 # could inadvertently update the PC.
1170 with m
.State("ISSUE_START"):
1171 # reset instruction fault
1172 sync
+= pdecode2
.instr_fault
.eq(0)
1173 # wait on "core stop" release, before next fetch
1174 # need to do this here, in case we are in a VL==0 loop
1175 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
1176 comb
+= fetch_pc_i_valid
.eq(1) # tell fetch to start
1177 with m
.If(fetch_pc_o_ready
): # fetch acknowledged us
1178 m
.next
= "INSN_WAIT"
1180 # tell core it's stopped, and acknowledge debug handshake
1181 comb
+= dbg
.core_stopped_i
.eq(1)
1182 # while stopped, allow updating SVSTATE
1183 with m
.If(self
.svstate_i
.ok
):
1184 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
1185 comb
+= self
.update_svstate
.eq(1)
1186 sync
+= self
.sv_changed
.eq(1)
1188 # wait for an instruction to arrive from Fetch
1189 with m
.State("INSN_WAIT"):
1190 # when using "single-step" mode, checking dbg.stopping_o
1191 # prevents progress. allow issue to proceed once started
1193 #if self.allow_overlap:
1194 # stopping = dbg.stopping_o
1195 with m
.If(stopping
):
1196 # stopping: jump back to idle
1197 m
.next
= "ISSUE_START"
1199 # request the icache to stop asserting "failed"
1200 comb
+= core
.icache
.flush_in
.eq(1)
1201 # stop instruction fault
1202 sync
+= pdecode2
.instr_fault
.eq(0)
1204 comb
+= fetch_insn_i_ready
.eq(1)
1205 with m
.If(fetch_insn_o_valid
):
1206 # loop into ISSUE_START if it's a SVP64 instruction
1207 # and VL == 0. this because VL==0 is a for-loop
1208 # from 0 to 0 i.e. always, always a NOP.
1209 cur_vl
= cur_state
.svstate
.vl
1210 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
1211 # update the PC before fetching the next instruction
1212 # since we are in a VL==0 loop, no instruction was
1213 # executed that we could be overwriting
1214 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1215 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1216 comb
+= self
.insn_done
.eq(1)
1217 m
.next
= "ISSUE_START"
1220 m
.next
= "PRED_START" # fetching predicate
1222 m
.next
= "DECODE_SV" # skip predication
1224 with m
.State("PRED_START"):
1225 comb
+= pred_insn_i_valid
.eq(1) # tell fetch_pred to start
1226 with m
.If(pred_insn_o_ready
): # fetch_pred acknowledged us
1227 m
.next
= "MASK_WAIT"
1229 with m
.State("MASK_WAIT"):
1230 comb
+= pred_mask_i_ready
.eq(1) # ready to receive the masks
1231 with m
.If(pred_mask_o_valid
): # predication masks are ready
1232 m
.next
= "PRED_SKIP"
1234 # skip zeros in predicate
1235 with m
.State("PRED_SKIP"):
1236 with m
.If(~is_svp64_mode
):
1237 m
.next
= "DECODE_SV" # nothing to do
1240 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
1241 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
1243 # new srcstep, after skipping zeros
1244 skip_srcstep
= Signal
.like(cur_srcstep
)
1245 # value to be added to the current srcstep
1246 src_delta
= Signal
.like(cur_srcstep
)
1247 # add leading zeros to srcstep, if not in zero mode
1248 with m
.If(~pred_src_zero
):
1249 # priority encoder (count leading zeros)
1250 # append guard bit, in case the mask is all zeros
1251 pri_enc_src
= PriorityEncoder(65)
1252 m
.submodules
.pri_enc_src
= pri_enc_src
1253 comb
+= pri_enc_src
.i
.eq(Cat(self
.srcmask
,
1255 comb
+= src_delta
.eq(pri_enc_src
.o
)
1256 # apply delta to srcstep
1257 comb
+= skip_srcstep
.eq(cur_srcstep
+ src_delta
)
1258 # shift-out all leading zeros from the mask
1259 # plus the leading "one" bit
1260 # TODO count leading zeros and shift-out the zero
1261 # bits, in the same step, in hardware
1262 sync
+= self
.srcmask
.eq(self
.srcmask
>> (src_delta
+1))
1264 # same as above, but for dststep
1265 skip_dststep
= Signal
.like(cur_dststep
)
1266 dst_delta
= Signal
.like(cur_dststep
)
1267 with m
.If(~pred_dst_zero
):
1268 pri_enc_dst
= PriorityEncoder(65)
1269 m
.submodules
.pri_enc_dst
= pri_enc_dst
1270 comb
+= pri_enc_dst
.i
.eq(Cat(self
.dstmask
,
1272 comb
+= dst_delta
.eq(pri_enc_dst
.o
)
1273 comb
+= skip_dststep
.eq(cur_dststep
+ dst_delta
)
1274 sync
+= self
.dstmask
.eq(self
.dstmask
>> (dst_delta
+1))
1276 # TODO: initialize mask[VL]=1 to avoid passing past VL
1277 with m
.If((skip_srcstep
>= cur_vl
) |
1278 (skip_dststep
>= cur_vl
)):
1279 # end of VL loop. Update PC and reset src/dst step
1280 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1281 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1282 comb
+= new_svstate
.srcstep
.eq(0)
1283 comb
+= new_svstate
.dststep
.eq(0)
1284 comb
+= self
.update_svstate
.eq(1)
1285 # synchronize with the simulator
1286 comb
+= self
.insn_done
.eq(1)
1288 m
.next
= "ISSUE_START"
1290 # update new src/dst step
1291 comb
+= new_svstate
.srcstep
.eq(skip_srcstep
)
1292 comb
+= new_svstate
.dststep
.eq(skip_dststep
)
1293 comb
+= self
.update_svstate
.eq(1)
1295 m
.next
= "DECODE_SV"
1297 # pass predicate mask bits through to satellite decoders
1298 # TODO: for SIMD this will be *multiple* bits
1299 sync
+= core
.i
.sv_pred_sm
.eq(self
.srcmask
[0])
1300 sync
+= core
.i
.sv_pred_dm
.eq(self
.dstmask
[0])
1302 # after src/dst step have been updated, we are ready
1303 # to decode the instruction
1304 with m
.State("DECODE_SV"):
1305 # decode the instruction
1306 with m
.If(~fetch_failed
):
1307 sync
+= pdecode2
.instr_fault
.eq(0)
1308 sync
+= core
.i
.e
.eq(pdecode2
.e
)
1309 sync
+= core
.i
.state
.eq(cur_state
)
1310 sync
+= core
.i
.raw_insn_i
.eq(dec_opcode_i
)
1311 sync
+= core
.i
.bigendian_i
.eq(self
.core_bigendian_i
)
1313 sync
+= core
.i
.sv_rm
.eq(pdecode2
.sv_rm
)
1314 # set RA_OR_ZERO detection in satellite decoders
1315 sync
+= core
.i
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
1316 # and svp64 detection
1317 sync
+= core
.i
.is_svp64_mode
.eq(is_svp64_mode
)
1318 # and svp64 bit-rev'd ldst mode
1319 ldst_dec
= pdecode2
.use_svp64_ldst_dec
1320 sync
+= core
.i
.use_svp64_ldst_dec
.eq(ldst_dec
)
1321 # after decoding, reset any previous exception condition,
1322 # allowing it to be set again during the next execution
1323 sync
+= pdecode2
.ldst_exc
.eq(0)
1325 m
.next
= "INSN_EXECUTE" # move to "execute"
1327 # handshake with execution FSM, move to "wait" once acknowledged
1328 with m
.State("INSN_EXECUTE"):
1329 # when using "single-step" mode, checking dbg.stopping_o
1330 # prevents progress. allow execute to proceed once started
1332 #if self.allow_overlap:
1333 # stopping = dbg.stopping_o
1334 with m
.If(stopping
):
1335 # stopping: jump back to idle
1336 m
.next
= "ISSUE_START"
1338 # request the icache to stop asserting "failed"
1339 comb
+= core
.icache
.flush_in
.eq(1)
1340 # stop instruction fault
1341 sync
+= pdecode2
.instr_fault
.eq(0)
1343 comb
+= exec_insn_i_valid
.eq(1) # trigger execute
1344 with m
.If(exec_insn_o_ready
): # execute acknowledged us
1345 m
.next
= "EXECUTE_WAIT"
1347 with m
.State("EXECUTE_WAIT"):
1348 comb
+= exec_pc_i_ready
.eq(1)
1349 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
1350 # the exception info needs to be blatted into
1351 # pdecode.ldst_exc, and the instruction "re-run".
1352 # when ldst_exc.happened is set, the PowerDecoder2
1353 # reacts very differently: it re-writes the instruction
1354 # with a "trap" (calls PowerDecoder2.trap()) which
1355 # will *overwrite* whatever was requested and jump the
1356 # PC to the exception address, as well as alter MSR.
1357 # nothing else needs to be done other than to note
1358 # the change of PC and MSR (and, later, SVSTATE)
1359 with m
.If(exc_happened
):
1360 mmu
= core
.fus
.get_exc("mmu0")
1361 ldst
= core
.fus
.get_exc("ldst0")
1363 with m
.If(fetch_failed
):
1364 # instruction fetch: exception is from MMU
1365 # reset instr_fault (highest priority)
1366 sync
+= pdecode2
.ldst_exc
.eq(mmu
)
1367 sync
+= pdecode2
.instr_fault
.eq(0)
1369 # request icache to stop asserting "failed"
1370 comb
+= core
.icache
.flush_in
.eq(1)
1371 with m
.If(~fetch_failed
):
1372 # otherwise assume it was a LDST exception
1373 sync
+= pdecode2
.ldst_exc
.eq(ldst
)
1375 with m
.If(exec_pc_o_valid
):
1377 # was this the last loop iteration?
1379 cur_vl
= cur_state
.svstate
.vl
1380 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
1382 with m
.If(pdecode2
.instr_fault
):
1383 # reset instruction fault, try again
1384 sync
+= pdecode2
.instr_fault
.eq(0)
1385 m
.next
= "ISSUE_START"
1387 # return directly to Decode if Execute generated an
1389 with m
.Elif(pdecode2
.ldst_exc
.happened
):
1390 m
.next
= "DECODE_SV"
1392 # if MSR, PC or SVSTATE were changed by the previous
1393 # instruction, go directly back to Fetch, without
1394 # updating either MSR PC or SVSTATE
1395 with m
.Elif(self
.msr_changed | self
.pc_changed |
1397 m
.next
= "ISSUE_START"
1399 # also return to Fetch, when no output was a vector
1400 # (regardless of SRCSTEP and VL), or when the last
1401 # instruction was really the last one of the VL loop
1402 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
1403 # before going back to fetch, update the PC state
1404 # register with the NIA.
1405 # ok here we are not reading the branch unit.
1406 # TODO: this just blithely overwrites whatever
1407 # pipeline updated the PC
1408 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1409 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1410 # reset SRCSTEP before returning to Fetch
1412 with m
.If(pdecode2
.loop_continue
):
1413 comb
+= new_svstate
.srcstep
.eq(0)
1414 comb
+= new_svstate
.dststep
.eq(0)
1415 comb
+= self
.update_svstate
.eq(1)
1417 comb
+= new_svstate
.srcstep
.eq(0)
1418 comb
+= new_svstate
.dststep
.eq(0)
1419 comb
+= self
.update_svstate
.eq(1)
1420 m
.next
= "ISSUE_START"
1422 # returning to Execute? then, first update SRCSTEP
1424 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
1425 comb
+= new_svstate
.dststep
.eq(next_dststep
)
1426 comb
+= self
.update_svstate
.eq(1)
1427 # return to mask skip loop
1428 m
.next
= "PRED_SKIP"
1431 # check if svstate needs updating: if so, write it to State Regfile
1432 with m
.If(self
.update_svstate
):
1433 sync
+= cur_state
.svstate
.eq(self
.new_svstate
) # for next clock
1435 def execute_fsm(self
, m
, core
,
1436 exec_insn_i_valid
, exec_insn_o_ready
,
1437 exec_pc_o_valid
, exec_pc_i_ready
):
1440 execute FSM. this interacts with the "issue" FSM
1441 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
1442 (outgoing). SVP64 RM prefixes have already been set up by the
1443 "issue" phase, so execute is fairly straightforward.
1449 pdecode2
= self
.pdecode2
1452 core_busy_o
= core
.n
.o_data
.busy_o
# core is busy
1453 core_ivalid_i
= core
.p
.i_valid
# instruction is valid
1455 if hasattr(core
, "icache"):
1456 fetch_failed
= core
.icache
.i_out
.fetch_failed
1458 fetch_failed
= Const(0, 1)
1460 with m
.FSM(name
="exec_fsm"):
1462 # waiting for instruction bus (stays there until not busy)
1463 with m
.State("INSN_START"):
1464 comb
+= exec_insn_o_ready
.eq(1)
1465 with m
.If(exec_insn_i_valid
):
1466 comb
+= core_ivalid_i
.eq(1) # instruction is valid/issued
1467 sync
+= self
.sv_changed
.eq(0)
1468 sync
+= self
.pc_changed
.eq(0)
1469 sync
+= self
.msr_changed
.eq(0)
1470 with m
.If(core
.p
.o_ready
): # only move if accepted
1471 m
.next
= "INSN_ACTIVE" # move to "wait completion"
1473 # instruction started: must wait till it finishes
1474 with m
.State("INSN_ACTIVE"):
1475 # note changes to MSR, PC and SVSTATE, and DEC/TB
1476 # these last two are done together, and passed to the
1478 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.SVSTATE
)):
1479 sync
+= self
.sv_changed
.eq(1)
1480 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.MSR
)):
1481 sync
+= self
.msr_changed
.eq(1)
1482 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.PC
)):
1483 sync
+= self
.pc_changed
.eq(1)
1484 with m
.If((self
.state_spr
.wen
&
1485 ((1 << StateRegs
.DEC
) |
(1 << StateRegs
.TB
))).bool()):
1486 comb
+= self
.pause_dec_tb
.eq(1)
1487 with m
.If(~core_busy_o
): # instruction done!
1488 comb
+= exec_pc_o_valid
.eq(1)
1489 with m
.If(exec_pc_i_ready
):
1490 # when finished, indicate "done".
1491 # however, if there was an exception, the instruction
1492 # is *not* yet done. this is an implementation
1493 # detail: we choose to implement exceptions by
1494 # taking the exception information from the LDST
1495 # unit, putting that *back* into the PowerDecoder2,
1496 # and *re-running the entire instruction*.
1497 # if we erroneously indicate "done" here, it is as if
1498 # there were *TWO* instructions:
1499 # 1) the failed LDST 2) a TRAP.
1500 with m
.If(~pdecode2
.ldst_exc
.happened
&
1501 ~pdecode2
.instr_fault
):
1502 comb
+= self
.insn_done
.eq(1)
1503 m
.next
= "INSN_START" # back to fetch
1504 # terminate returns directly to INSN_START
1505 with m
.If(dbg
.terminate_i
):
1506 # comb += self.insn_done.eq(1) - no because it's not
1507 m
.next
= "INSN_START" # back to fetch
1509 def elaborate(self
, platform
):
1510 m
= super().elaborate(platform
)
1512 comb
, sync
= m
.d
.comb
, m
.d
.sync
1513 cur_state
= self
.cur_state
1514 pdecode2
= self
.pdecode2
1518 # set up peripherals and core
1519 core_rst
= self
.core_rst
1521 # indicate to outside world if any FU is still executing
1522 comb
+= self
.any_busy
.eq(core
.n
.o_data
.any_busy_o
) # any FU executing
1524 # address of the next instruction, in the absence of a branch
1525 # depends on the instruction size
1528 # connect up debug signals
1529 with m
.If(core
.o
.core_terminate_o
):
1530 comb
+= dbg
.terminate_i
.eq(1)
1532 # pass the prefix mode from Fetch to Issue, so the latter can loop
1534 is_svp64_mode
= Signal()
1536 # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1537 # issue, decode/execute, now joined by "Predicate fetch/calculate".
1538 # these are the handshake signals between each
1540 # fetch FSM can run as soon as the PC is valid
1541 fetch_pc_i_valid
= Signal() # Execute tells Fetch "start next read"
1542 fetch_pc_o_ready
= Signal() # Fetch Tells SVSTATE "proceed"
1544 # fetch FSM hands over the instruction to be decoded / issued
1545 fetch_insn_o_valid
= Signal()
1546 fetch_insn_i_ready
= Signal()
1548 # predicate fetch FSM decodes and fetches the predicate
1549 pred_insn_i_valid
= Signal()
1550 pred_insn_o_ready
= Signal()
1552 # predicate fetch FSM delivers the masks
1553 pred_mask_o_valid
= Signal()
1554 pred_mask_i_ready
= Signal()
1556 # issue FSM delivers the instruction to the be executed
1557 exec_insn_i_valid
= Signal()
1558 exec_insn_o_ready
= Signal()
1560 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1561 exec_pc_o_valid
= Signal()
1562 exec_pc_i_ready
= Signal()
1564 # the FSMs here are perhaps unusual in that they detect conditions
1565 # then "hold" information, combinatorially, for the core
1566 # (as opposed to using sync - which would be on a clock's delay)
1567 # this includes the actual opcode, valid flags and so on.
1569 # Fetch, then predicate fetch, then Issue, then Execute.
1570 # Issue is where the VL for-loop # lives. the ready/valid
1571 # signalling is used to communicate between the four.
1573 self
.fetch_fsm(m
, dbg
, core
, dbg
.state
.pc
, dbg
.state
.msr
,
1574 dbg
.state
.svstate
, nia
, is_svp64_mode
,
1575 fetch_pc_o_ready
, fetch_pc_i_valid
,
1576 fetch_insn_o_valid
, fetch_insn_i_ready
)
1578 self
.issue_fsm(m
, core
, nia
,
1579 dbg
, core_rst
, is_svp64_mode
,
1580 fetch_pc_o_ready
, fetch_pc_i_valid
,
1581 fetch_insn_o_valid
, fetch_insn_i_ready
,
1582 pred_insn_i_valid
, pred_insn_o_ready
,
1583 pred_mask_o_valid
, pred_mask_i_ready
,
1584 exec_insn_i_valid
, exec_insn_o_ready
,
1585 exec_pc_o_valid
, exec_pc_i_ready
)
1588 self
.fetch_predicate_fsm(m
,
1589 pred_insn_i_valid
, pred_insn_o_ready
,
1590 pred_mask_o_valid
, pred_mask_i_ready
)
1592 self
.execute_fsm(m
, core
,
1593 exec_insn_i_valid
, exec_insn_o_ready
,
1594 exec_pc_o_valid
, exec_pc_i_ready
)
1596 # whatever was done above, over-ride it if core reset is held
1597 with m
.If(core_rst
):
1603 class TestIssuer(Elaboratable
):
1604 def __init__(self
, pspec
):
1605 self
.ti
= TestIssuerInternal(pspec
)
1606 self
.pll
= DummyPLL(instance
=True)
1608 self
.dbg_rst_i
= Signal(reset_less
=True)
1610 # PLL direct clock or not
1611 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1613 self
.pll_test_o
= Signal(reset_less
=True)
1614 self
.pll_vco_o
= Signal(reset_less
=True)
1615 self
.clk_sel_i
= Signal(2, reset_less
=True)
1616 self
.ref_clk
= ClockSignal() # can't rename it but that's ok
1617 self
.pllclk_clk
= ClockSignal("pllclk")
1619 def elaborate(self
, platform
):
1623 # TestIssuer nominally runs at main clock, actually it is
1624 # all combinatorial internally except for coresync'd components
1625 m
.submodules
.ti
= ti
= self
.ti
1628 # ClockSelect runs at PLL output internal clock rate
1629 m
.submodules
.wrappll
= pll
= self
.pll
1631 # add clock domains from PLL
1632 cd_pll
= ClockDomain("pllclk")
1635 # PLL clock established. has the side-effect of running clklsel
1636 # at the PLL's speed (see DomainRenamer("pllclk") above)
1637 pllclk
= self
.pllclk_clk
1638 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1640 # wire up external 24mhz to PLL
1641 #comb += pll.clk_24_i.eq(self.ref_clk)
1642 # output 18 mhz PLL test signal, and analog oscillator out
1643 comb
+= self
.pll_test_o
.eq(pll
.pll_test_o
)
1644 comb
+= self
.pll_vco_o
.eq(pll
.pll_vco_o
)
1646 # input to pll clock selection
1647 comb
+= pll
.clk_sel_i
.eq(self
.clk_sel_i
)
1649 # now wire up ResetSignals. don't mind them being in this domain
1650 pll_rst
= ResetSignal("pllclk")
1651 comb
+= pll_rst
.eq(ResetSignal())
1653 # internal clock is set to selector clock-out. has the side-effect of
1654 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1655 # debug clock runs at coresync internal clock
1656 if self
.ti
.dbg_domain
!= 'sync':
1657 cd_dbgsync
= ClockDomain("dbgsync")
1658 intclk
= ClockSignal(self
.ti
.core_domain
)
1659 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1660 # XXX BYPASS PLL XXX
1661 # XXX BYPASS PLL XXX
1662 # XXX BYPASS PLL XXX
1664 comb
+= intclk
.eq(self
.ref_clk
)
1665 assert self
.ti
.core_domain
!= 'sync', \
1666 "cannot set core_domain to sync and use pll at the same time"
1668 if self
.ti
.core_domain
!= 'sync':
1669 comb
+= intclk
.eq(ClockSignal())
1670 if self
.ti
.dbg_domain
!= 'sync':
1671 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1672 comb
+= dbgclk
.eq(intclk
)
1673 comb
+= self
.ti
.dbg_rst_i
.eq(self
.dbg_rst_i
)
1678 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1679 [ClockSignal(), ResetSignal()]
1681 def external_ports(self
):
1682 ports
= self
.ti
.external_ports()
1683 ports
.append(ClockSignal())
1684 ports
.append(ResetSignal())
1686 ports
.append(self
.clk_sel_i
)
1687 ports
.append(self
.pll
.clk_24_i
)
1688 ports
.append(self
.pll_test_o
)
1689 ports
.append(self
.pll_vco_o
)
1690 ports
.append(self
.pllclk_clk
)
1691 ports
.append(self
.ref_clk
)
1695 if __name__
== '__main__':
1696 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1702 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1703 imem_ifacetype
='bare_wb',
1708 dut
= TestIssuer(pspec
)
1709 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1711 if len(sys
.argv
) == 1:
1712 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1713 with
open("test_issuer.il", "w") as f
: