a80941dbd26e01ff6cc014cb1fab1531ff509fda
3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
, Repl
, Cat
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from nmutil
.singlepipe
import ControlBase
25 from soc
.simple
.core_data
import FetchOutput
, FetchInput
27 from nmigen
.lib
.coding
import PriorityEncoder
29 from openpower
.decoder
.power_decoder
import create_pdecode
30 from openpower
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
31 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
32 from openpower
.decoder
.decode2execute1
import Data
33 from openpower
.decoder
.power_enums
import (MicrOp
, SVP64PredInt
, SVP64PredCR
,
35 from openpower
.state
import CoreState
36 from openpower
.consts
import (CR
, SVP64CROffs
, MSR
)
37 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
38 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
39 from soc
.simple
.core
import NonProductionCore
40 from soc
.config
.test
.test_loadstore
import TestMemPspec
41 from soc
.config
.ifetch
import ConfigFetchUnit
42 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
43 from soc
.debug
.jtag
import JTAG
44 from soc
.config
.pinouts
import get_pinspecs
45 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
46 from soc
.bus
.simple_gpio
import SimpleGPIO
47 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
48 from soc
.clock
.select
import ClockSelect
49 from soc
.clock
.dummypll
import DummyPLL
50 from openpower
.sv
.svstate
import SVSTATERec
51 from soc
.experiment
.icache
import ICache
53 from nmutil
.util
import rising_edge
56 def get_insn(f_instr_o
, pc
):
57 if f_instr_o
.width
== 32:
60 # 64-bit: bit 2 of pc decides which word to select
61 return f_instr_o
.word_select(pc
[2], 32)
63 # gets state input or reads from state regfile
66 def state_get(m
, res
, core_rst
, state_i
, name
, regfile
, regnum
):
69 # read the {insert state variable here}
70 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
72 sync
+= res_ok_delay
.eq(~state_i
.ok
)
73 with m
.If(state_i
.ok
):
74 # incoming override (start from pc_i)
75 comb
+= res
.eq(state_i
.data
)
77 # otherwise read StateRegs regfile for {insert state here}...
78 comb
+= regfile
.ren
.eq(1 << regnum
)
79 # ... but on a 1-clock delay
80 with m
.If(res_ok_delay
):
81 comb
+= res
.eq(regfile
.o_data
)
84 def get_predint(m
, mask
, name
):
85 """decode SVP64 predicate integer mask field to reg number and invert
86 this is identical to the equivalent function in ISACaller except that
87 it doesn't read the INT directly, it just decodes "what needs to be done"
88 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
90 * all1s is set to indicate that no mask is to be applied.
91 * regread indicates the GPR register number to be read
92 * invert is set to indicate that the register value is to be inverted
93 * unary indicates that the contents of the register is to be shifted 1<<r3
96 regread
= Signal(5, name
=name
+"regread")
97 invert
= Signal(name
=name
+"invert")
98 unary
= Signal(name
=name
+"unary")
99 all1s
= Signal(name
=name
+"all1s")
101 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
102 comb
+= all1s
.eq(1) # use 0b1111 (all ones)
103 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
104 comb
+= regread
.eq(3)
105 comb
+= unary
.eq(1) # 1<<r3 - shift r3 (single bit)
106 with m
.Case(SVP64PredInt
.R3
.value
):
107 comb
+= regread
.eq(3)
108 with m
.Case(SVP64PredInt
.R3_N
.value
):
109 comb
+= regread
.eq(3)
111 with m
.Case(SVP64PredInt
.R10
.value
):
112 comb
+= regread
.eq(10)
113 with m
.Case(SVP64PredInt
.R10_N
.value
):
114 comb
+= regread
.eq(10)
116 with m
.Case(SVP64PredInt
.R30
.value
):
117 comb
+= regread
.eq(30)
118 with m
.Case(SVP64PredInt
.R30_N
.value
):
119 comb
+= regread
.eq(30)
121 return regread
, invert
, unary
, all1s
124 def get_predcr(m
, mask
, name
):
125 """decode SVP64 predicate CR to reg number field and invert status
126 this is identical to _get_predcr in ISACaller
129 idx
= Signal(2, name
=name
+"idx")
130 invert
= Signal(name
=name
+"crinvert")
132 with m
.Case(SVP64PredCR
.LT
.value
):
133 comb
+= idx
.eq(CR
.LT
)
135 with m
.Case(SVP64PredCR
.GE
.value
):
136 comb
+= idx
.eq(CR
.LT
)
138 with m
.Case(SVP64PredCR
.GT
.value
):
139 comb
+= idx
.eq(CR
.GT
)
141 with m
.Case(SVP64PredCR
.LE
.value
):
142 comb
+= idx
.eq(CR
.GT
)
144 with m
.Case(SVP64PredCR
.EQ
.value
):
145 comb
+= idx
.eq(CR
.EQ
)
147 with m
.Case(SVP64PredCR
.NE
.value
):
148 comb
+= idx
.eq(CR
.EQ
)
150 with m
.Case(SVP64PredCR
.SO
.value
):
151 comb
+= idx
.eq(CR
.SO
)
153 with m
.Case(SVP64PredCR
.NS
.value
):
154 comb
+= idx
.eq(CR
.SO
)
159 class TestIssuerBase(Elaboratable
):
160 """TestIssuerBase - common base class for Issuers
162 takes care of power-on reset, peripherals, debug, DEC/TB,
163 and gets PC/MSR/SVSTATE from the State Regfile etc.
166 def __init__(self
, pspec
):
168 # test if microwatt compatibility is to be enabled
169 self
.microwatt_compat
= (hasattr(pspec
, "microwatt_compat") and
170 (pspec
.microwatt_compat
== True))
171 self
.alt_reset
= Signal(reset_less
=True) # not connected yet (microwatt)
173 if self
.microwatt_compat
:
174 self
.microwatt_old
= False
175 self
.microwatt_debug
= True # set to False when using an FPGA
177 # test is SVP64 is to be enabled
178 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
180 # and if regfiles are reduced
181 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
182 (pspec
.regreduce
== True))
184 # and if overlap requested
185 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
186 (pspec
.allow_overlap
== True))
188 # and get the core domain
189 self
.core_domain
= "coresync"
190 if (hasattr(pspec
, "core_domain") and
191 isinstance(pspec
.core_domain
, str)):
192 self
.core_domain
= pspec
.core_domain
194 # JTAG interface. add this right at the start because if it's
195 # added it *modifies* the pspec, by adding enable/disable signals
196 # for parts of the rest of the core
197 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
198 #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
199 self
.dbg_domain
= "dbgsync" # domain for DMI/JTAG clock
201 # XXX MUST keep this up-to-date with litex, and
202 # soc-cocotb-sim, and err.. all needs sorting out, argh
205 'eint', 'gpio', 'mspi0',
206 # 'mspi1', - disabled for now
207 # 'pwm', 'sd0', - disabled for now
209 self
.jtag
= JTAG(get_pinspecs(subset
=subset
),
210 domain
=self
.dbg_domain
)
211 # add signals to pspec to enable/disable icache and dcache
212 # (or data and intstruction wishbone if icache/dcache not included)
213 # https://bugs.libre-soc.org/show_bug.cgi?id=520
214 # TODO: do we actually care if these are not domain-synchronised?
215 # honestly probably not.
216 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
217 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
218 self
.wb_sram_en
= self
.jtag
.wb_sram_en
220 self
.wb_sram_en
= Const(1)
222 # add 4k sram blocks?
223 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
224 pspec
.sram4x4kblock
== True)
228 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
232 # add interrupt controller?
233 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
235 self
.xics_icp
= XICS_ICP()
236 self
.xics_ics
= XICS_ICS()
237 self
.int_level_i
= self
.xics_ics
.int_level_i
239 self
.ext_irq
= Signal()
241 # add GPIO peripheral?
242 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
244 self
.simple_gpio
= SimpleGPIO()
245 self
.gpio_o
= self
.simple_gpio
.gpio_o
247 # main instruction core. suitable for prototyping / demo only
248 self
.core
= core
= NonProductionCore(pspec
)
249 self
.core_rst
= ResetSignal(self
.core_domain
)
251 # instruction decoder. goes into Trap Record
252 #pdecode = create_pdecode()
253 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
254 self
.pdecode2
= PowerDecode2(None, state
=self
.cur_state
,
255 opkls
=IssuerDecode2ToOperand
,
256 svp64_en
=self
.svp64_en
,
257 regreduce_en
=self
.regreduce_en
)
258 pdecode
= self
.pdecode2
.dec
261 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
263 self
.update_svstate
= Signal() # set this if updating svstate
264 self
.new_svstate
= new_svstate
= SVSTATERec("new_svstate")
266 # Test Instruction memory
267 if hasattr(core
, "icache"):
268 # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
269 # truly dreadful. needs a huge reorg.
270 pspec
.icache
= core
.icache
271 self
.imem
= ConfigFetchUnit(pspec
).fu
274 self
.dbg
= CoreDebug()
275 self
.dbg_rst_i
= Signal(reset_less
=True)
277 # instruction go/monitor
278 self
.pc_o
= Signal(64, reset_less
=True)
279 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
280 self
.msr_i
= Data(64, "msr_i") # set "ok" to indicate "please change me"
281 self
.svstate_i
= Data(64, "svstate_i") # ditto
282 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
283 self
.busy_o
= Signal(reset_less
=True)
284 self
.memerr_o
= Signal(reset_less
=True)
286 # STATE regfile read /write ports for PC, MSR, SVSTATE
287 staterf
= self
.core
.regs
.rf
['state']
288 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
289 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
290 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
292 self
.state_w_msr
= staterf
.w_ports
['d_wr2'] # MSR wr
293 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
294 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
296 # DMI interface access
297 intrf
= self
.core
.regs
.rf
['int']
298 fastrf
= self
.core
.regs
.rf
['fast']
299 crrf
= self
.core
.regs
.rf
['cr']
300 xerrf
= self
.core
.regs
.rf
['xer']
301 self
.int_r
= intrf
.r_ports
['dmi'] # INT DMI read
302 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR DMI read
303 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER DMI read
304 self
.fast_r
= fastrf
.r_ports
['dmi'] # FAST DMI read
308 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
309 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
311 # hack method of keeping an eye on whether branch/trap set the PC
312 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
313 self
.state_nia
.wen
.name
= 'state_nia_wen'
314 # and whether SPR pipeline sets DEC or TB
315 self
.state_spr
= self
.core
.regs
.rf
['state'].w_ports
['state1']
317 # pulse to synchronize the simulator at instruction end
318 self
.insn_done
= Signal()
320 # indicate any instruction still outstanding, in execution
321 self
.any_busy
= Signal()
324 # store copies of predicate masks
325 self
.srcmask
= Signal(64)
326 self
.dstmask
= Signal(64)
328 # sigh, the wishbone addresses are not wishbone-compliant
329 # in old versions of microwatt, tplaten_3d_game is a new one
330 if self
.microwatt_compat
:
331 self
.ibus_adr
= Signal(32, name
='wishbone_insn_out.adr')
332 self
.dbus_adr
= Signal(32, name
='wishbone_data_out.adr')
334 # add an output of the PC and instruction, and whether it was requested
335 # this is for verilator debug purposes
336 if self
.microwatt_compat
:
337 self
.nia
= Signal(64)
338 self
.msr_o
= Signal(64)
339 self
.nia_req
= Signal(1)
340 self
.insn
= Signal(32)
341 self
.ldst_req
= Signal(1)
342 self
.ldst_addr
= Signal(1)
344 # for pausing dec/tb during an SPR pipeline event, this
345 # ensures that an SPR write (mtspr) to TB or DEC does not
346 # get overwritten by the DEC/TB FSM
347 self
.pause_dec_tb
= Signal()
349 def setup_peripherals(self
, m
):
350 comb
, sync
= m
.d
.comb
, m
.d
.sync
352 # okaaaay so the debug module must be in coresync clock domain
353 # but NOT its reset signal. to cope with this, set every single
354 # submodule explicitly in coresync domain, debug and JTAG
355 # in their own one but using *external* reset.
356 csd
= DomainRenamer(self
.core_domain
)
357 dbd
= DomainRenamer(self
.dbg_domain
)
359 if self
.microwatt_compat
:
360 m
.submodules
.core
= core
= self
.core
362 m
.submodules
.core
= core
= csd(self
.core
)
364 # this _so_ needs sorting out. ICache is added down inside
365 # LoadStore1 and is already a submodule of LoadStore1
366 if not isinstance(self
.imem
, ICache
):
367 m
.submodules
.imem
= imem
= csd(self
.imem
)
369 # set up JTAG Debug Module (in correct domain)
370 m
.submodules
.dbg
= dbg
= dbd(self
.dbg
)
372 m
.submodules
.jtag
= jtag
= dbd(self
.jtag
)
373 # TODO: UART2GDB mux, here, from external pin
374 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
375 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
377 # fixup the clocks in microwatt-compat mode (but leave resets alone
378 # so that microwatt soc.vhdl can pull a reset on the core or DMI
379 # can do it, just like in TestIssuer)
380 if self
.microwatt_compat
:
381 intclk
= ClockSignal(self
.core_domain
)
382 dbgclk
= ClockSignal(self
.dbg_domain
)
383 if self
.core_domain
!= 'sync':
384 comb
+= intclk
.eq(ClockSignal())
385 if self
.dbg_domain
!= 'sync':
386 comb
+= dbgclk
.eq(ClockSignal())
388 # if using old version of microwatt
389 # drop the first 3 bits of the incoming wishbone addresses
390 if self
.microwatt_compat
:
391 ibus
= self
.imem
.ibus
392 dbus
= self
.core
.l0
.cmpi
.wb_bus()
393 if self
.microwatt_old
:
394 comb
+= self
.ibus_adr
.eq(Cat(Const(0, 3), ibus
.adr
))
395 comb
+= self
.dbus_adr
.eq(Cat(Const(0, 3), dbus
.adr
))
397 comb
+= self
.ibus_adr
.eq(ibus
.adr
)
398 comb
+= self
.dbus_adr
.eq(dbus
.adr
)
399 if self
.microwatt_debug
:
400 # microwatt verilator debug purposes
401 pi
= self
.core
.l0
.cmpi
.pi
.pi
402 comb
+= self
.ldst_req
.eq(pi
.addr_ok_o
)
403 comb
+= self
.ldst_addr
.eq(pi
.addr
)
405 cur_state
= self
.cur_state
407 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
409 for i
, sram
in enumerate(self
.sram4k
):
410 m
.submodules
["sram4k_%d" % i
] = csd(sram
)
411 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
413 # XICS interrupt handler
415 m
.submodules
.xics_icp
= icp
= csd(self
.xics_icp
)
416 m
.submodules
.xics_ics
= ics
= csd(self
.xics_ics
)
417 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
418 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
420 sync
+= cur_state
.eint
.eq(self
.ext_irq
) # connect externally
422 # GPIO test peripheral
424 m
.submodules
.simple_gpio
= simple_gpio
= csd(self
.simple_gpio
)
426 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
427 # XXX causes litex ECP5 test to get wrong idea about input and output
428 # (but works with verilator sim *sigh*)
429 # if self.gpio and self.xics:
430 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
432 # instruction decoder
433 pdecode
= create_pdecode()
434 m
.submodules
.dec2
= pdecode2
= csd(self
.pdecode2
)
436 m
.submodules
.svp64
= svp64
= csd(self
.svp64
)
438 # clock delay power-on reset
439 cd_por
= ClockDomain(reset_less
=True)
440 cd_sync
= ClockDomain()
441 m
.domains
+= cd_por
, cd_sync
442 core_sync
= ClockDomain(self
.core_domain
)
443 if self
.core_domain
!= "sync":
444 m
.domains
+= core_sync
445 if self
.dbg_domain
!= "sync":
446 dbg_sync
= ClockDomain(self
.dbg_domain
)
447 m
.domains
+= dbg_sync
449 # create a delay, but remember it is in the power-on-reset clock domain!
450 ti_rst
= Signal(reset_less
=True)
451 delay
= Signal(range(4), reset
=3)
452 stop_delay
= Signal(range(16), reset
=5)
453 with m
.If(delay
!= 0):
454 m
.d
.por
+= delay
.eq(delay
- 1) # decrement... in POR domain!
455 with m
.If(stop_delay
!= 0):
456 m
.d
.por
+= stop_delay
.eq(stop_delay
- 1) # likewise
457 comb
+= cd_por
.clk
.eq(ClockSignal())
459 # power-on reset delay
460 core_rst
= ResetSignal(self
.core_domain
)
461 if self
.core_domain
!= "sync":
462 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
463 comb
+= core_rst
.eq(ti_rst
)
465 with m
.If(delay
!= 0 | dbg
.core_rst_o
):
466 comb
+= core_rst
.eq(1)
467 with m
.If(stop_delay
!= 0):
468 # run DMI core-stop as well but on an extra couple of cycles
469 comb
+= dbg
.core_stopped_i
.eq(1)
471 # connect external reset signal to DMI Reset
472 if self
.dbg_domain
!= "sync":
473 dbg_rst
= ResetSignal(self
.dbg_domain
)
474 comb
+= dbg_rst
.eq(self
.dbg_rst_i
)
476 # busy/halted signals from core
477 core_busy_o
= ~core
.p
.o_ready | core
.n
.o_data
.busy_o
# core is busy
478 comb
+= self
.busy_o
.eq(core_busy_o
)
479 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
481 # temporary hack: says "go" immediately for both address gen and ST
482 # XXX: st.go_i is set to 1 cycle delay to reduce combinatorial chains
484 ldst
= core
.fus
.fus
['ldst0']
485 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
486 # link addr-go direct to rel
487 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
)
488 m
.d
.sync
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
490 def do_dmi(self
, m
, dbg
):
491 """deals with DMI debug requests
493 currently only provides read requests for the INT regfile, CR and XER
494 it will later also deal with *writing* to these regfiles.
498 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
500 intrf
= self
.core
.regs
.rf
['int']
501 fastrf
= self
.core
.regs
.rf
['fast']
503 with m
.If(d_reg
.req
): # request for regfile access being made
504 # TODO: error-check this
505 # XXX should this be combinatorial? sync better?
507 comb
+= self
.int_r
.ren
.eq(1 << d_reg
.addr
)
509 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
510 comb
+= self
.int_r
.ren
.eq(1)
511 d_reg_delay
= Signal()
512 sync
+= d_reg_delay
.eq(d_reg
.req
)
513 with m
.If(d_reg_delay
):
514 # data arrives one clock later
515 comb
+= d_reg
.data
.eq(self
.int_r
.o_data
)
516 comb
+= d_reg
.ack
.eq(1)
519 with m
.If(d_fast
.req
): # request for regfile access being made
521 comb
+= self
.fast_r
.ren
.eq(1 << d_fast
.addr
)
523 comb
+= self
.fast_r
.addr
.eq(d_fast
.addr
)
524 comb
+= self
.fast_r
.ren
.eq(1)
525 d_fast_delay
= Signal()
526 sync
+= d_fast_delay
.eq(d_fast
.req
)
527 with m
.If(d_fast_delay
):
528 # data arrives one clock later
529 comb
+= d_fast
.data
.eq(self
.fast_r
.o_data
)
530 comb
+= d_fast
.ack
.eq(1)
532 # sigh same thing for CR debug
533 with m
.If(d_cr
.req
): # request for regfile access being made
534 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
535 d_cr_delay
= Signal()
536 sync
+= d_cr_delay
.eq(d_cr
.req
)
537 with m
.If(d_cr_delay
):
538 # data arrives one clock later
539 comb
+= d_cr
.data
.eq(self
.cr_r
.o_data
)
540 comb
+= d_cr
.ack
.eq(1)
543 with m
.If(d_xer
.req
): # request for regfile access being made
544 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
545 d_xer_delay
= Signal()
546 sync
+= d_xer_delay
.eq(d_xer
.req
)
547 with m
.If(d_xer_delay
):
548 # data arrives one clock later
549 comb
+= d_xer
.data
.eq(self
.xer_r
.o_data
)
550 comb
+= d_xer
.ack
.eq(1)
552 def tb_dec_fsm(self
, m
, spr_dec
):
555 this is a FSM for updating either dec or tb. it runs alternately
556 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
557 value to DEC, however the regfile has "passthrough" on it so this
560 see v3.0B p1097-1099 for Timer Resource and p1065 and p1076
563 comb
, sync
= m
.d
.comb
, m
.d
.sync
564 state_rf
= self
.core
.regs
.rf
['state']
565 state_r_dectb
= state_rf
.r_ports
['issue'] # DEC/TB
566 state_w_dectb
= state_rf
.w_ports
['issue'] # DEC/TB
570 # initiates read of current DEC
571 with m
.State("DEC_READ"):
572 comb
+= state_r_dectb
.ren
.eq(1<<StateRegs
.DEC
)
573 with m
.If(~self
.pause_dec_tb
):
576 # waits for DEC read to arrive (1 cycle), updates with new value
577 # respects if dec/tb writing has been paused
578 with m
.State("DEC_WRITE"):
579 with m
.If(self
.pause_dec_tb
):
580 # if paused, return to reading
584 # TODO: MSR.LPCR 32-bit decrement mode
585 comb
+= new_dec
.eq(state_r_dectb
.o_data
- 1)
586 comb
+= state_w_dectb
.wen
.eq(1<<StateRegs
.DEC
)
587 comb
+= state_w_dectb
.i_data
.eq(new_dec
)
588 # copy to cur_state for decoder, for an interrupt
589 sync
+= spr_dec
.eq(new_dec
)
592 # initiates read of current TB
593 with m
.State("TB_READ"):
594 comb
+= state_r_dectb
.ren
.eq(1<<StateRegs
.TB
)
595 with m
.If(~self
.pause_dec_tb
):
598 # waits for read TB to arrive, initiates write of current TB
599 # respects if dec/tb writing has been paused
600 with m
.State("TB_WRITE"):
601 with m
.If(self
.pause_dec_tb
):
602 # if paused, return to reading
606 comb
+= new_tb
.eq(state_r_dectb
.o_data
+ 1)
607 comb
+= state_w_dectb
.wen
.eq(1<<StateRegs
.TB
)
608 comb
+= state_w_dectb
.i_data
.eq(new_tb
)
613 def elaborate(self
, platform
):
616 comb
, sync
= m
.d
.comb
, m
.d
.sync
617 cur_state
= self
.cur_state
618 pdecode2
= self
.pdecode2
621 # set up peripherals and core
622 core_rst
= self
.core_rst
623 self
.setup_peripherals(m
)
625 # reset current state if core reset requested
627 m
.d
.sync
+= self
.cur_state
.eq(0)
628 # and, sigh, set configured values, which are also done in regfile
629 m
.d
.sync
+= self
.cur_state
.pc
.eq(self
.core
.pc_at_reset
)
630 m
.d
.sync
+= self
.cur_state
.msr
.eq(self
.core
.msr_at_reset
)
632 # check halted condition: requested PC to execute matches DMI stop addr
633 # and immediately stop. address of 0xffff_ffff_ffff_ffff can never
636 comb
+= halted
.eq(dbg
.stop_addr_o
== dbg
.state
.pc
)
638 comb
+= dbg
.core_stopped_i
.eq(1)
639 comb
+= dbg
.terminate_i
.eq(1)
641 # PC and instruction from I-Memory
642 comb
+= self
.pc_o
.eq(cur_state
.pc
)
643 self
.pc_changed
= Signal() # note write to PC
644 self
.msr_changed
= Signal() # note write to MSR
645 self
.sv_changed
= Signal() # note write to SVSTATE
647 # read state either from incoming override or from regfile
648 state
= CoreState("get") # current state (MSR/PC/SVSTATE)
649 state_get(m
, state
.msr
, core_rst
, self
.msr_i
,
651 self
.state_r_msr
, StateRegs
.MSR
)
652 state_get(m
, state
.pc
, core_rst
, self
.pc_i
,
654 self
.state_r_pc
, StateRegs
.PC
)
655 state_get(m
, state
.svstate
, core_rst
, self
.svstate_i
,
656 "svstate", # read SVSTATE
657 self
.state_r_sv
, StateRegs
.SVSTATE
)
659 # don't write pc every cycle
660 comb
+= self
.state_w_pc
.wen
.eq(0)
661 comb
+= self
.state_w_pc
.i_data
.eq(0)
663 # connect up debug state. note "combinatorially same" below,
664 # this is a bit naff, passing state over in the dbg class, but
665 # because it is combinatorial it achieves the desired goal
666 comb
+= dbg
.state
.eq(state
)
668 # this bit doesn't have to be in the FSM: connect up to read
669 # regfiles on demand from DMI
672 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
673 # (which uses that in PowerDecoder2 to raise 0x900 exception)
674 self
.tb_dec_fsm(m
, cur_state
.dec
)
676 # while stopped, allow updating the MSR, PC and SVSTATE.
677 # these are mainly for debugging purposes (including DMI/JTAG)
678 with m
.If(dbg
.core_stopped_i
):
679 with m
.If(self
.pc_i
.ok
):
680 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
681 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
682 sync
+= self
.pc_changed
.eq(1)
683 with m
.If(self
.msr_i
.ok
):
684 comb
+= self
.state_w_msr
.wen
.eq(1 << StateRegs
.MSR
)
685 comb
+= self
.state_w_msr
.i_data
.eq(self
.msr_i
.data
)
686 sync
+= self
.msr_changed
.eq(1)
687 with m
.If(self
.svstate_i
.ok | self
.update_svstate
):
688 with m
.If(self
.svstate_i
.ok
): # over-ride from external source
689 comb
+= self
.new_svstate
.eq(self
.svstate_i
.data
)
690 comb
+= self
.state_w_sv
.wen
.eq(1 << StateRegs
.SVSTATE
)
691 comb
+= self
.state_w_sv
.i_data
.eq(self
.new_svstate
)
692 sync
+= self
.sv_changed
.eq(1)
694 # start renaming some of the ports to match microwatt
695 if self
.microwatt_compat
:
696 self
.core
.o
.core_terminate_o
.name
= "terminated_out"
697 # names of DMI interface
698 self
.dbg
.dmi
.addr_i
.name
= 'dmi_addr'
699 self
.dbg
.dmi
.din
.name
= 'dmi_din'
700 self
.dbg
.dmi
.dout
.name
= 'dmi_dout'
701 self
.dbg
.dmi
.req_i
.name
= 'dmi_req'
702 self
.dbg
.dmi
.we_i
.name
= 'dmi_wr'
703 self
.dbg
.dmi
.ack_o
.name
= 'dmi_ack'
704 # wishbone instruction bus
705 ibus
= self
.imem
.ibus
706 ibus
.adr
.name
= 'wishbone_insn_out.adr'
707 ibus
.dat_w
.name
= 'wishbone_insn_out.dat'
708 ibus
.sel
.name
= 'wishbone_insn_out.sel'
709 ibus
.cyc
.name
= 'wishbone_insn_out.cyc'
710 ibus
.stb
.name
= 'wishbone_insn_out.stb'
711 ibus
.we
.name
= 'wishbone_insn_out.we'
712 ibus
.dat_r
.name
= 'wishbone_insn_in.dat'
713 ibus
.ack
.name
= 'wishbone_insn_in.ack'
714 ibus
.stall
.name
= 'wishbone_insn_in.stall'
716 dbus
= self
.core
.l0
.cmpi
.wb_bus()
717 dbus
.adr
.name
= 'wishbone_data_out.adr'
718 dbus
.dat_w
.name
= 'wishbone_data_out.dat'
719 dbus
.sel
.name
= 'wishbone_data_out.sel'
720 dbus
.cyc
.name
= 'wishbone_data_out.cyc'
721 dbus
.stb
.name
= 'wishbone_data_out.stb'
722 dbus
.we
.name
= 'wishbone_data_out.we'
723 dbus
.dat_r
.name
= 'wishbone_data_in.dat'
724 dbus
.ack
.name
= 'wishbone_data_in.ack'
725 dbus
.stall
.name
= 'wishbone_data_in.stall'
730 yield from self
.pc_i
.ports()
731 yield from self
.msr_i
.ports()
734 yield from self
.core
.ports()
735 yield from self
.imem
.ports()
736 yield self
.core_bigendian_i
742 def external_ports(self
):
743 if self
.microwatt_compat
:
744 ports
= [self
.core
.o
.core_terminate_o
,
746 self
.alt_reset
, # not connected yet
747 self
.nia
, self
.insn
, self
.nia_req
, self
.msr_o
,
748 self
.ldst_req
, self
.ldst_addr
,
752 ports
+= list(self
.dbg
.dmi
.ports())
753 # for dbus/ibus microwatt, exclude err btw and cti
754 for name
, sig
in self
.imem
.ibus
.fields
.items():
755 if name
not in ['err', 'bte', 'cti', 'adr']:
757 for name
, sig
in self
.core
.l0
.cmpi
.wb_bus().fields
.items():
758 if name
not in ['err', 'bte', 'cti', 'adr']:
760 # microwatt non-compliant with wishbone
761 ports
.append(self
.ibus_adr
)
762 ports
.append(self
.dbus_adr
)
765 ports
= self
.pc_i
.ports()
766 ports
= self
.msr_i
.ports()
767 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
771 ports
+= list(self
.jtag
.external_ports())
773 # don't add DMI if JTAG is enabled
774 ports
+= list(self
.dbg
.dmi
.ports())
776 ports
+= list(self
.imem
.ibus
.fields
.values())
777 ports
+= list(self
.core
.l0
.cmpi
.wb_bus().fields
.values())
780 for sram
in self
.sram4k
:
781 ports
+= list(sram
.bus
.fields
.values())
784 ports
+= list(self
.xics_icp
.bus
.fields
.values())
785 ports
+= list(self
.xics_ics
.bus
.fields
.values())
786 ports
.append(self
.int_level_i
)
788 ports
.append(self
.ext_irq
)
791 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
792 ports
.append(self
.gpio_o
)
800 class TestIssuerInternal(TestIssuerBase
):
801 """TestIssuer - reads instructions from TestMemory and issues them
803 efficiency and speed is not the main goal here: functional correctness
804 and code clarity is. optimisations (which almost 100% interfere with
805 easy understanding) come later.
808 def fetch_fsm(self
, m
, dbg
, core
, nia
, is_svp64_mode
,
809 fetch_pc_o_ready
, fetch_pc_i_valid
,
810 fetch_insn_o_valid
, fetch_insn_i_ready
):
813 this FSM performs fetch of raw instruction data, partial-decodes
814 it 32-bit at a time to detect SVP64 prefixes, and will optionally
815 read a 2nd 32-bit quantity if that occurs.
819 pdecode2
= self
.pdecode2
820 cur_state
= self
.cur_state
821 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
822 pc
, msr
, svstate
= cur_state
.pc
, cur_state
.msr
, cur_state
.svstate
824 # also note instruction fetch failed
825 if hasattr(core
, "icache"):
826 fetch_failed
= core
.icache
.i_out
.fetch_failed
829 fetch_failed
= Const(0, 1)
832 # set priv / virt mode on I-Cache, sigh
833 if isinstance(self
.imem
, ICache
):
834 comb
+= self
.imem
.i_in
.priv_mode
.eq(~msr
[MSR
.PR
])
835 comb
+= self
.imem
.i_in
.virt_mode
.eq(msr
[MSR
.IR
]) # Instr. Redir (VM)
837 with m
.FSM(name
='fetch_fsm'):
839 # allow fetch to not run at startup due to I-Cache reset not
840 # having time to settle. power-on-reset holds dbg.core_stopped_i
841 with m
.State("PRE_IDLE"):
842 with m
.If(~dbg
.core_stopped_i
& ~dbg
.core_stop_o
):
846 with m
.State("IDLE"):
847 # fetch allowed if not failed and stopped but not stepping
848 # (see dmi.py for how core_stop_o is generated)
849 with m
.If(~fetch_failed
& ~dbg
.core_stop_o
):
850 comb
+= fetch_pc_o_ready
.eq(1)
851 with m
.If(fetch_pc_i_valid
& ~pdecode2
.instr_fault
853 # instruction allowed to go: start by reading the PC
854 # capture the PC and also drop it into Insn Memory
855 # we have joined a pair of combinatorial memory
856 # lookups together. this is Generally Bad.
857 comb
+= self
.imem
.a_pc_i
.eq(pc
)
858 comb
+= self
.imem
.a_i_valid
.eq(1)
859 comb
+= self
.imem
.f_i_valid
.eq(1)
860 m
.next
= "INSN_READ" # move to "wait for bus" phase
862 # dummy pause to find out why simulation is not keeping up
863 with m
.State("INSN_READ"):
864 # when using "single-step" mode, checking dbg.stopping_o
865 # prevents progress. allow fetch to proceed once started
867 #if self.allow_overlap:
868 # stopping = dbg.stopping_o
870 # stopping: jump back to idle
873 with m
.If(self
.imem
.f_busy_o
&
874 ~pdecode2
.instr_fault
): # zzz...
875 # busy but not fetch failed: stay in wait-read
876 comb
+= self
.imem
.a_pc_i
.eq(pc
)
877 comb
+= self
.imem
.a_i_valid
.eq(1)
878 comb
+= self
.imem
.f_i_valid
.eq(1)
880 # not busy (or fetch failed!): instruction fetched
881 # when fetch failed, the instruction gets ignored
883 if hasattr(core
, "icache"):
884 # blech, icache returns actual instruction
885 insn
= self
.imem
.f_instr_o
887 # but these return raw memory
888 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
891 # decode the SVP64 prefix, if any
892 comb
+= svp64
.raw_opcode_in
.eq(insn
)
893 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
894 # pass the decoded prefix (if any) to PowerDecoder2
895 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
896 sync
+= pdecode2
.is_svp64_mode
.eq(is_svp64_mode
)
897 # remember whether this is a prefixed instruction,
898 # so the FSM can readily loop when VL==0
899 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
900 # calculate the address of the following instruction
901 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
902 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
903 with m
.If(~svp64
.is_svp64_mode
):
904 # with no prefix, store the instruction
905 # and hand it directly to the next FSM
906 sync
+= dec_opcode_i
.eq(insn
)
907 m
.next
= "INSN_READY"
909 # fetch the rest of the instruction from memory
910 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
911 comb
+= self
.imem
.a_i_valid
.eq(1)
912 comb
+= self
.imem
.f_i_valid
.eq(1)
913 m
.next
= "INSN_READ2"
915 # not SVP64 - 32-bit only
916 sync
+= nia
.eq(cur_state
.pc
+ 4)
917 sync
+= dec_opcode_i
.eq(insn
)
918 if self
.microwatt_compat
:
919 # for verilator debug purposes
920 comb
+= self
.insn
.eq(insn
)
921 comb
+= self
.nia
.eq(cur_state
.pc
)
922 comb
+= self
.msr_o
.eq(cur_state
.msr
)
923 comb
+= self
.nia_req
.eq(1)
924 m
.next
= "INSN_READY"
926 with m
.State("INSN_READ2"):
927 with m
.If(self
.imem
.f_busy_o
): # zzz...
928 # busy: stay in wait-read
929 comb
+= self
.imem
.a_i_valid
.eq(1)
930 comb
+= self
.imem
.f_i_valid
.eq(1)
932 # not busy: instruction fetched
933 if hasattr(core
, "icache"):
934 # blech, icache returns actual instruction
935 insn
= self
.imem
.f_instr_o
937 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
938 sync
+= dec_opcode_i
.eq(insn
)
939 m
.next
= "INSN_READY"
940 # TODO: probably can start looking at pdecode2.rm_dec
941 # here or maybe even in INSN_READ state, if svp64_mode
942 # detected, in order to trigger - and wait for - the
945 pmode
= pdecode2
.rm_dec
.predmode
947 if pmode != SVP64PredMode.ALWAYS.value:
948 fire predicate loading FSM and wait before
951 sync += self.srcmask.eq(-1) # set to all 1s
952 sync += self.dstmask.eq(-1) # set to all 1s
953 m.next = "INSN_READY"
956 with m
.State("INSN_READY"):
957 # hand over the instruction, to be decoded
958 comb
+= fetch_insn_o_valid
.eq(1)
959 with m
.If(fetch_insn_i_ready
):
963 def fetch_predicate_fsm(self
, m
,
964 pred_insn_i_valid
, pred_insn_o_ready
,
965 pred_mask_o_valid
, pred_mask_i_ready
):
966 """fetch_predicate_fsm - obtains (constructs in the case of CR)
967 src/dest predicate masks
969 https://bugs.libre-soc.org/show_bug.cgi?id=617
970 the predicates can be read here, by using IntRegs r_ports['pred']
971 or CRRegs r_ports['pred']. in the case of CRs it will have to
972 be done through multiple reads, extracting one relevant at a time.
973 later, a faster way would be to use the 32-bit-wide CR port but
974 this is more complex decoding, here. equivalent code used in
975 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
977 note: this ENTIRE FSM is not to be called when svp64 is disabled
981 pdecode2
= self
.pdecode2
982 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
983 predmode
= rm_dec
.predmode
984 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
985 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
986 # get src/dst step, so we can skip already used mask bits
987 cur_state
= self
.cur_state
988 srcstep
= cur_state
.svstate
.srcstep
989 dststep
= cur_state
.svstate
.dststep
990 cur_vl
= cur_state
.svstate
.vl
993 sregread
, sinvert
, sunary
, sall1s
= get_predint(m
, srcpred
, 's')
994 dregread
, dinvert
, dunary
, dall1s
= get_predint(m
, dstpred
, 'd')
995 sidx
, scrinvert
= get_predcr(m
, srcpred
, 's')
996 didx
, dcrinvert
= get_predcr(m
, dstpred
, 'd')
998 # store fetched masks, for either intpred or crpred
999 # when src/dst step is not zero, the skipped mask bits need to be
1000 # shifted-out, before actually storing them in src/dest mask
1001 new_srcmask
= Signal(64, reset_less
=True)
1002 new_dstmask
= Signal(64, reset_less
=True)
1004 with m
.FSM(name
="fetch_predicate"):
1006 with m
.State("FETCH_PRED_IDLE"):
1007 comb
+= pred_insn_o_ready
.eq(1)
1008 with m
.If(pred_insn_i_valid
):
1009 with m
.If(predmode
== SVP64PredMode
.INT
):
1010 # skip fetching destination mask register, when zero
1012 sync
+= new_dstmask
.eq(-1)
1013 # directly go to fetch source mask register
1014 # guaranteed not to be zero (otherwise predmode
1015 # would be SVP64PredMode.ALWAYS, not INT)
1016 comb
+= int_pred
.addr
.eq(sregread
)
1017 comb
+= int_pred
.ren
.eq(1)
1018 m
.next
= "INT_SRC_READ"
1019 # fetch destination predicate register
1021 comb
+= int_pred
.addr
.eq(dregread
)
1022 comb
+= int_pred
.ren
.eq(1)
1023 m
.next
= "INT_DST_READ"
1024 with m
.Elif(predmode
== SVP64PredMode
.CR
):
1025 # go fetch masks from the CR register file
1026 sync
+= new_srcmask
.eq(0)
1027 sync
+= new_dstmask
.eq(0)
1030 sync
+= self
.srcmask
.eq(-1)
1031 sync
+= self
.dstmask
.eq(-1)
1032 m
.next
= "FETCH_PRED_DONE"
1034 with m
.State("INT_DST_READ"):
1035 # store destination mask
1036 inv
= Repl(dinvert
, 64)
1038 # set selected mask bit for 1<<r3 mode
1039 dst_shift
= Signal(range(64))
1040 comb
+= dst_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1041 sync
+= new_dstmask
.eq(1 << dst_shift
)
1043 # invert mask if requested
1044 sync
+= new_dstmask
.eq(self
.int_pred
.o_data ^ inv
)
1045 # skip fetching source mask register, when zero
1047 sync
+= new_srcmask
.eq(-1)
1048 m
.next
= "FETCH_PRED_SHIFT_MASK"
1049 # fetch source predicate register
1051 comb
+= int_pred
.addr
.eq(sregread
)
1052 comb
+= int_pred
.ren
.eq(1)
1053 m
.next
= "INT_SRC_READ"
1055 with m
.State("INT_SRC_READ"):
1057 inv
= Repl(sinvert
, 64)
1059 # set selected mask bit for 1<<r3 mode
1060 src_shift
= Signal(range(64))
1061 comb
+= src_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1062 sync
+= new_srcmask
.eq(1 << src_shift
)
1064 # invert mask if requested
1065 sync
+= new_srcmask
.eq(self
.int_pred
.o_data ^ inv
)
1066 m
.next
= "FETCH_PRED_SHIFT_MASK"
1068 # fetch masks from the CR register file
1069 # implements the following loop:
1070 # idx, inv = get_predcr(mask)
1072 # for cr_idx in range(vl):
1073 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle
1075 # mask |= 1 << cr_idx
1077 with m
.State("CR_READ"):
1078 # CR index to be read, which will be ready by the next cycle
1079 cr_idx
= Signal
.like(cur_vl
, reset_less
=True)
1080 # submit the read operation to the regfile
1081 with m
.If(cr_idx
!= cur_vl
):
1082 # the CR read port is unary ...
1084 # ... in MSB0 convention ...
1085 # ren = 1 << (7 - cr_idx)
1086 # ... and with an offset:
1087 # ren = 1 << (7 - off - cr_idx)
1088 idx
= SVP64CROffs
.CRPred
+ cr_idx
1089 comb
+= cr_pred
.ren
.eq(1 << (7 - idx
))
1090 # signal data valid in the next cycle
1091 cr_read
= Signal(reset_less
=True)
1092 sync
+= cr_read
.eq(1)
1093 # load the next index
1094 sync
+= cr_idx
.eq(cr_idx
+ 1)
1097 sync
+= cr_read
.eq(0)
1098 sync
+= cr_idx
.eq(0)
1099 m
.next
= "FETCH_PRED_SHIFT_MASK"
1101 # compensate for the one cycle delay on the regfile
1102 cur_cr_idx
= Signal
.like(cur_vl
)
1103 comb
+= cur_cr_idx
.eq(cr_idx
- 1)
1104 # read the CR field, select the appropriate bit
1105 cr_field
= Signal(4)
1108 comb
+= cr_field
.eq(cr_pred
.o_data
)
1109 comb
+= scr_bit
.eq(cr_field
.bit_select(sidx
, 1)
1111 comb
+= dcr_bit
.eq(cr_field
.bit_select(didx
, 1)
1113 # set the corresponding mask bit
1114 bit_to_set
= Signal
.like(self
.srcmask
)
1115 comb
+= bit_to_set
.eq(1 << cur_cr_idx
)
1117 sync
+= new_srcmask
.eq(new_srcmask | bit_to_set
)
1119 sync
+= new_dstmask
.eq(new_dstmask | bit_to_set
)
1121 with m
.State("FETCH_PRED_SHIFT_MASK"):
1122 # shift-out skipped mask bits
1123 sync
+= self
.srcmask
.eq(new_srcmask
>> srcstep
)
1124 sync
+= self
.dstmask
.eq(new_dstmask
>> dststep
)
1125 m
.next
= "FETCH_PRED_DONE"
1127 with m
.State("FETCH_PRED_DONE"):
1128 comb
+= pred_mask_o_valid
.eq(1)
1129 with m
.If(pred_mask_i_ready
):
1130 m
.next
= "FETCH_PRED_IDLE"
1132 def issue_fsm(self
, m
, core
, nia
,
1133 dbg
, core_rst
, is_svp64_mode
,
1134 fetch_pc_o_ready
, fetch_pc_i_valid
,
1135 fetch_insn_o_valid
, fetch_insn_i_ready
,
1136 pred_insn_i_valid
, pred_insn_o_ready
,
1137 pred_mask_o_valid
, pred_mask_i_ready
,
1138 exec_insn_i_valid
, exec_insn_o_ready
,
1139 exec_pc_o_valid
, exec_pc_i_ready
):
1142 decode / issue FSM. this interacts with the "fetch" FSM
1143 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
1144 (outgoing). also interacts with the "execute" FSM
1145 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
1147 SVP64 RM prefixes have already been set up by the
1148 "fetch" phase, so execute is fairly straightforward.
1153 pdecode2
= self
.pdecode2
1154 cur_state
= self
.cur_state
1155 new_svstate
= self
.new_svstate
1158 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
1160 # for updating svstate (things like srcstep etc.)
1161 comb
+= new_svstate
.eq(cur_state
.svstate
)
1163 # precalculate srcstep+1 and dststep+1
1164 cur_srcstep
= cur_state
.svstate
.srcstep
1165 cur_dststep
= cur_state
.svstate
.dststep
1166 next_srcstep
= Signal
.like(cur_srcstep
)
1167 next_dststep
= Signal
.like(cur_dststep
)
1168 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
1169 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
1171 # note if an exception happened. in a pipelined or OoO design
1172 # this needs to be accompanied by "shadowing" (or stalling)
1173 exc_happened
= self
.core
.o
.exc_happened
1174 # also note instruction fetch failed
1175 if hasattr(core
, "icache"):
1176 fetch_failed
= core
.icache
.i_out
.fetch_failed
1178 # set to fault in decoder
1179 # update (highest priority) instruction fault
1180 rising_fetch_failed
= rising_edge(m
, fetch_failed
)
1181 with m
.If(rising_fetch_failed
):
1182 sync
+= pdecode2
.instr_fault
.eq(1)
1184 fetch_failed
= Const(0, 1)
1185 flush_needed
= False
1187 sync
+= fetch_pc_i_valid
.eq(0)
1189 with m
.FSM(name
="issue_fsm"):
1191 # sync with the "fetch" phase which is reading the instruction
1192 # at this point, there is no instruction running, that
1193 # could inadvertently update the PC.
1194 with m
.State("ISSUE_START"):
1195 # reset instruction fault
1196 sync
+= pdecode2
.instr_fault
.eq(0)
1197 # wait on "core stop" release, before next fetch
1198 # need to do this here, in case we are in a VL==0 loop
1199 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
1200 sync
+= fetch_pc_i_valid
.eq(1) # tell fetch to start
1201 sync
+= cur_state
.pc
.eq(dbg
.state
.pc
)
1202 sync
+= cur_state
.svstate
.eq(dbg
.state
.svstate
)
1203 sync
+= cur_state
.msr
.eq(dbg
.state
.msr
)
1204 with m
.If(fetch_pc_o_ready
): # fetch acknowledged us
1205 m
.next
= "INSN_WAIT"
1207 # tell core it's stopped, and acknowledge debug handshake
1208 comb
+= dbg
.core_stopped_i
.eq(1)
1209 # while stopped, allow updating SVSTATE
1210 with m
.If(self
.svstate_i
.ok
):
1211 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
1212 comb
+= self
.update_svstate
.eq(1)
1213 sync
+= self
.sv_changed
.eq(1)
1215 # wait for an instruction to arrive from Fetch
1216 with m
.State("INSN_WAIT"):
1217 # when using "single-step" mode, checking dbg.stopping_o
1218 # prevents progress. allow issue to proceed once started
1220 #if self.allow_overlap:
1221 # stopping = dbg.stopping_o
1222 with m
.If(stopping
):
1223 # stopping: jump back to idle
1224 m
.next
= "ISSUE_START"
1226 # request the icache to stop asserting "failed"
1227 comb
+= core
.icache
.flush_in
.eq(1)
1228 # stop instruction fault
1229 sync
+= pdecode2
.instr_fault
.eq(0)
1231 comb
+= fetch_insn_i_ready
.eq(1)
1232 with m
.If(fetch_insn_o_valid
):
1233 # loop into ISSUE_START if it's a SVP64 instruction
1234 # and VL == 0. this because VL==0 is a for-loop
1235 # from 0 to 0 i.e. always, always a NOP.
1236 cur_vl
= cur_state
.svstate
.vl
1237 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
1238 # update the PC before fetching the next instruction
1239 # since we are in a VL==0 loop, no instruction was
1240 # executed that we could be overwriting
1241 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1242 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1243 comb
+= self
.insn_done
.eq(1)
1244 m
.next
= "ISSUE_START"
1247 m
.next
= "PRED_START" # fetching predicate
1249 m
.next
= "DECODE_SV" # skip predication
1251 with m
.State("PRED_START"):
1252 comb
+= pred_insn_i_valid
.eq(1) # tell fetch_pred to start
1253 with m
.If(pred_insn_o_ready
): # fetch_pred acknowledged us
1254 m
.next
= "MASK_WAIT"
1256 with m
.State("MASK_WAIT"):
1257 comb
+= pred_mask_i_ready
.eq(1) # ready to receive the masks
1258 with m
.If(pred_mask_o_valid
): # predication masks are ready
1259 m
.next
= "PRED_SKIP"
1261 # skip zeros in predicate
1262 with m
.State("PRED_SKIP"):
1263 with m
.If(~is_svp64_mode
):
1264 m
.next
= "DECODE_SV" # nothing to do
1267 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
1268 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
1270 # new srcstep, after skipping zeros
1271 skip_srcstep
= Signal
.like(cur_srcstep
)
1272 # value to be added to the current srcstep
1273 src_delta
= Signal
.like(cur_srcstep
)
1274 # add leading zeros to srcstep, if not in zero mode
1275 with m
.If(~pred_src_zero
):
1276 # priority encoder (count leading zeros)
1277 # append guard bit, in case the mask is all zeros
1278 pri_enc_src
= PriorityEncoder(65)
1279 m
.submodules
.pri_enc_src
= pri_enc_src
1280 comb
+= pri_enc_src
.i
.eq(Cat(self
.srcmask
,
1282 comb
+= src_delta
.eq(pri_enc_src
.o
)
1283 # apply delta to srcstep
1284 comb
+= skip_srcstep
.eq(cur_srcstep
+ src_delta
)
1285 # shift-out all leading zeros from the mask
1286 # plus the leading "one" bit
1287 # TODO count leading zeros and shift-out the zero
1288 # bits, in the same step, in hardware
1289 sync
+= self
.srcmask
.eq(self
.srcmask
>> (src_delta
+1))
1291 # same as above, but for dststep
1292 skip_dststep
= Signal
.like(cur_dststep
)
1293 dst_delta
= Signal
.like(cur_dststep
)
1294 with m
.If(~pred_dst_zero
):
1295 pri_enc_dst
= PriorityEncoder(65)
1296 m
.submodules
.pri_enc_dst
= pri_enc_dst
1297 comb
+= pri_enc_dst
.i
.eq(Cat(self
.dstmask
,
1299 comb
+= dst_delta
.eq(pri_enc_dst
.o
)
1300 comb
+= skip_dststep
.eq(cur_dststep
+ dst_delta
)
1301 sync
+= self
.dstmask
.eq(self
.dstmask
>> (dst_delta
+1))
1303 # TODO: initialize mask[VL]=1 to avoid passing past VL
1304 with m
.If((skip_srcstep
>= cur_vl
) |
1305 (skip_dststep
>= cur_vl
)):
1306 # end of VL loop. Update PC and reset src/dst step
1307 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1308 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1309 comb
+= new_svstate
.srcstep
.eq(0)
1310 comb
+= new_svstate
.dststep
.eq(0)
1311 comb
+= self
.update_svstate
.eq(1)
1312 # synchronize with the simulator
1313 comb
+= self
.insn_done
.eq(1)
1315 m
.next
= "ISSUE_START"
1317 # update new src/dst step
1318 comb
+= new_svstate
.srcstep
.eq(skip_srcstep
)
1319 comb
+= new_svstate
.dststep
.eq(skip_dststep
)
1320 comb
+= self
.update_svstate
.eq(1)
1322 m
.next
= "DECODE_SV"
1324 # pass predicate mask bits through to satellite decoders
1325 # TODO: for SIMD this will be *multiple* bits
1326 sync
+= core
.i
.sv_pred_sm
.eq(self
.srcmask
[0])
1327 sync
+= core
.i
.sv_pred_dm
.eq(self
.dstmask
[0])
1329 # after src/dst step have been updated, we are ready
1330 # to decode the instruction
1331 with m
.State("DECODE_SV"):
1332 # decode the instruction
1333 with m
.If(~fetch_failed
):
1334 sync
+= pdecode2
.instr_fault
.eq(0)
1335 sync
+= core
.i
.e
.eq(pdecode2
.e
)
1336 sync
+= core
.i
.state
.eq(cur_state
)
1337 sync
+= core
.i
.raw_insn_i
.eq(dec_opcode_i
)
1338 sync
+= core
.i
.bigendian_i
.eq(self
.core_bigendian_i
)
1340 sync
+= core
.i
.sv_rm
.eq(pdecode2
.sv_rm
)
1341 # set RA_OR_ZERO detection in satellite decoders
1342 sync
+= core
.i
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
1343 # and svp64 detection
1344 sync
+= core
.i
.is_svp64_mode
.eq(is_svp64_mode
)
1345 # and svp64 bit-rev'd ldst mode
1346 ldst_dec
= pdecode2
.use_svp64_ldst_dec
1347 sync
+= core
.i
.use_svp64_ldst_dec
.eq(ldst_dec
)
1348 # after decoding, reset any previous exception condition,
1349 # allowing it to be set again during the next execution
1350 sync
+= pdecode2
.ldst_exc
.eq(0)
1352 m
.next
= "INSN_EXECUTE" # move to "execute"
1354 # handshake with execution FSM, move to "wait" once acknowledged
1355 with m
.State("INSN_EXECUTE"):
1356 # when using "single-step" mode, checking dbg.stopping_o
1357 # prevents progress. allow execute to proceed once started
1359 #if self.allow_overlap:
1360 # stopping = dbg.stopping_o
1361 with m
.If(stopping
):
1362 # stopping: jump back to idle
1363 m
.next
= "ISSUE_START"
1365 # request the icache to stop asserting "failed"
1366 comb
+= core
.icache
.flush_in
.eq(1)
1367 # stop instruction fault
1368 sync
+= pdecode2
.instr_fault
.eq(0)
1370 comb
+= exec_insn_i_valid
.eq(1) # trigger execute
1371 with m
.If(exec_insn_o_ready
): # execute acknowledged us
1372 m
.next
= "EXECUTE_WAIT"
1374 with m
.State("EXECUTE_WAIT"):
1375 comb
+= exec_pc_i_ready
.eq(1)
1376 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
1377 # the exception info needs to be blatted into
1378 # pdecode.ldst_exc, and the instruction "re-run".
1379 # when ldst_exc.happened is set, the PowerDecoder2
1380 # reacts very differently: it re-writes the instruction
1381 # with a "trap" (calls PowerDecoder2.trap()) which
1382 # will *overwrite* whatever was requested and jump the
1383 # PC to the exception address, as well as alter MSR.
1384 # nothing else needs to be done other than to note
1385 # the change of PC and MSR (and, later, SVSTATE)
1386 with m
.If(exc_happened
):
1387 mmu
= core
.fus
.get_exc("mmu0")
1388 ldst
= core
.fus
.get_exc("ldst0")
1390 with m
.If(fetch_failed
):
1391 # instruction fetch: exception is from MMU
1392 # reset instr_fault (highest priority)
1393 sync
+= pdecode2
.ldst_exc
.eq(mmu
)
1394 sync
+= pdecode2
.instr_fault
.eq(0)
1396 # request icache to stop asserting "failed"
1397 comb
+= core
.icache
.flush_in
.eq(1)
1398 with m
.If(~fetch_failed
):
1399 # otherwise assume it was a LDST exception
1400 sync
+= pdecode2
.ldst_exc
.eq(ldst
)
1402 with m
.If(exec_pc_o_valid
):
1404 # was this the last loop iteration?
1406 cur_vl
= cur_state
.svstate
.vl
1407 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
1409 with m
.If(pdecode2
.instr_fault
):
1410 # reset instruction fault, try again
1411 sync
+= pdecode2
.instr_fault
.eq(0)
1412 m
.next
= "ISSUE_START"
1414 # return directly to Decode if Execute generated an
1416 with m
.Elif(pdecode2
.ldst_exc
.happened
):
1417 m
.next
= "DECODE_SV"
1419 # if MSR, PC or SVSTATE were changed by the previous
1420 # instruction, go directly back to Fetch, without
1421 # updating either MSR PC or SVSTATE
1422 with m
.Elif(self
.msr_changed | self
.pc_changed |
1424 m
.next
= "ISSUE_START"
1426 # also return to Fetch, when no output was a vector
1427 # (regardless of SRCSTEP and VL), or when the last
1428 # instruction was really the last one of the VL loop
1429 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
1430 # before going back to fetch, update the PC state
1431 # register with the NIA.
1432 # ok here we are not reading the branch unit.
1433 # TODO: this just blithely overwrites whatever
1434 # pipeline updated the PC
1435 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1436 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1437 # reset SRCSTEP before returning to Fetch
1439 with m
.If(pdecode2
.loop_continue
):
1440 comb
+= new_svstate
.srcstep
.eq(0)
1441 comb
+= new_svstate
.dststep
.eq(0)
1442 comb
+= self
.update_svstate
.eq(1)
1444 comb
+= new_svstate
.srcstep
.eq(0)
1445 comb
+= new_svstate
.dststep
.eq(0)
1446 comb
+= self
.update_svstate
.eq(1)
1447 m
.next
= "ISSUE_START"
1449 # returning to Execute? then, first update SRCSTEP
1451 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
1452 comb
+= new_svstate
.dststep
.eq(next_dststep
)
1453 comb
+= self
.update_svstate
.eq(1)
1454 # return to mask skip loop
1455 m
.next
= "PRED_SKIP"
1458 # check if svstate needs updating: if so, write it to State Regfile
1459 with m
.If(self
.update_svstate
):
1460 sync
+= cur_state
.svstate
.eq(self
.new_svstate
) # for next clock
1462 def execute_fsm(self
, m
, core
,
1463 exec_insn_i_valid
, exec_insn_o_ready
,
1464 exec_pc_o_valid
, exec_pc_i_ready
):
1467 execute FSM. this interacts with the "issue" FSM
1468 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
1469 (outgoing). SVP64 RM prefixes have already been set up by the
1470 "issue" phase, so execute is fairly straightforward.
1476 pdecode2
= self
.pdecode2
1479 core_busy_o
= core
.n
.o_data
.busy_o
# core is busy
1480 core_ivalid_i
= core
.p
.i_valid
# instruction is valid
1482 if hasattr(core
, "icache"):
1483 fetch_failed
= core
.icache
.i_out
.fetch_failed
1485 fetch_failed
= Const(0, 1)
1487 with m
.FSM(name
="exec_fsm"):
1489 # waiting for instruction bus (stays there until not busy)
1490 with m
.State("INSN_START"):
1491 comb
+= exec_insn_o_ready
.eq(1)
1492 with m
.If(exec_insn_i_valid
):
1493 comb
+= core_ivalid_i
.eq(1) # instruction is valid/issued
1494 sync
+= self
.sv_changed
.eq(0)
1495 sync
+= self
.pc_changed
.eq(0)
1496 sync
+= self
.msr_changed
.eq(0)
1497 with m
.If(core
.p
.o_ready
): # only move if accepted
1498 m
.next
= "INSN_ACTIVE" # move to "wait completion"
1500 # instruction started: must wait till it finishes
1501 with m
.State("INSN_ACTIVE"):
1502 # note changes to MSR, PC and SVSTATE, and DEC/TB
1503 # these last two are done together, and passed to the
1505 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.SVSTATE
)):
1506 sync
+= self
.sv_changed
.eq(1)
1507 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.MSR
)):
1508 sync
+= self
.msr_changed
.eq(1)
1509 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.PC
)):
1510 sync
+= self
.pc_changed
.eq(1)
1511 with m
.If((self
.state_spr
.wen
&
1512 ((1 << StateRegs
.DEC
) |
(1 << StateRegs
.TB
))).bool()):
1513 comb
+= self
.pause_dec_tb
.eq(1)
1514 with m
.If(~core_busy_o
): # instruction done!
1515 comb
+= exec_pc_o_valid
.eq(1)
1516 with m
.If(exec_pc_i_ready
):
1517 # when finished, indicate "done".
1518 # however, if there was an exception, the instruction
1519 # is *not* yet done. this is an implementation
1520 # detail: we choose to implement exceptions by
1521 # taking the exception information from the LDST
1522 # unit, putting that *back* into the PowerDecoder2,
1523 # and *re-running the entire instruction*.
1524 # if we erroneously indicate "done" here, it is as if
1525 # there were *TWO* instructions:
1526 # 1) the failed LDST 2) a TRAP.
1527 with m
.If(~pdecode2
.ldst_exc
.happened
&
1528 ~pdecode2
.instr_fault
):
1529 comb
+= self
.insn_done
.eq(1)
1530 m
.next
= "INSN_START" # back to fetch
1531 # terminate returns directly to INSN_START
1532 with m
.If(dbg
.terminate_i
):
1533 # comb += self.insn_done.eq(1) - no because it's not
1534 m
.next
= "INSN_START" # back to fetch
1536 def elaborate(self
, platform
):
1537 m
= super().elaborate(platform
)
1539 comb
, sync
= m
.d
.comb
, m
.d
.sync
1540 cur_state
= self
.cur_state
1541 pdecode2
= self
.pdecode2
1545 # set up peripherals and core
1546 core_rst
= self
.core_rst
1548 # indicate to outside world if any FU is still executing
1549 comb
+= self
.any_busy
.eq(core
.n
.o_data
.any_busy_o
) # any FU executing
1551 # address of the next instruction, in the absence of a branch
1552 # depends on the instruction size
1555 # connect up debug signals
1556 with m
.If(core
.o
.core_terminate_o
):
1557 comb
+= dbg
.terminate_i
.eq(1)
1559 # pass the prefix mode from Fetch to Issue, so the latter can loop
1561 is_svp64_mode
= Signal()
1563 # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1564 # issue, decode/execute, now joined by "Predicate fetch/calculate".
1565 # these are the handshake signals between each
1567 # fetch FSM can run as soon as the PC is valid
1568 fetch_pc_i_valid
= Signal() # Execute tells Fetch "start next read"
1569 fetch_pc_o_ready
= Signal() # Fetch Tells SVSTATE "proceed"
1571 # fetch FSM hands over the instruction to be decoded / issued
1572 fetch_insn_o_valid
= Signal()
1573 fetch_insn_i_ready
= Signal()
1575 # predicate fetch FSM decodes and fetches the predicate
1576 pred_insn_i_valid
= Signal()
1577 pred_insn_o_ready
= Signal()
1579 # predicate fetch FSM delivers the masks
1580 pred_mask_o_valid
= Signal()
1581 pred_mask_i_ready
= Signal()
1583 # issue FSM delivers the instruction to the be executed
1584 exec_insn_i_valid
= Signal()
1585 exec_insn_o_ready
= Signal()
1587 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1588 exec_pc_o_valid
= Signal()
1589 exec_pc_i_ready
= Signal()
1591 # the FSMs here are perhaps unusual in that they detect conditions
1592 # then "hold" information, combinatorially, for the core
1593 # (as opposed to using sync - which would be on a clock's delay)
1594 # this includes the actual opcode, valid flags and so on.
1596 # Fetch, then predicate fetch, then Issue, then Execute.
1597 # Issue is where the VL for-loop # lives. the ready/valid
1598 # signalling is used to communicate between the four.
1600 self
.fetch_fsm(m
, dbg
, core
, nia
, is_svp64_mode
,
1601 fetch_pc_o_ready
, fetch_pc_i_valid
,
1602 fetch_insn_o_valid
, fetch_insn_i_ready
)
1604 self
.issue_fsm(m
, core
, nia
,
1605 dbg
, core_rst
, is_svp64_mode
,
1606 fetch_pc_o_ready
, fetch_pc_i_valid
,
1607 fetch_insn_o_valid
, fetch_insn_i_ready
,
1608 pred_insn_i_valid
, pred_insn_o_ready
,
1609 pred_mask_o_valid
, pred_mask_i_ready
,
1610 exec_insn_i_valid
, exec_insn_o_ready
,
1611 exec_pc_o_valid
, exec_pc_i_ready
)
1614 self
.fetch_predicate_fsm(m
,
1615 pred_insn_i_valid
, pred_insn_o_ready
,
1616 pred_mask_o_valid
, pred_mask_i_ready
)
1618 self
.execute_fsm(m
, core
,
1619 exec_insn_i_valid
, exec_insn_o_ready
,
1620 exec_pc_o_valid
, exec_pc_i_ready
)
1622 # whatever was done above, over-ride it if core reset is held
1623 with m
.If(core_rst
):
1629 class TestIssuer(Elaboratable
):
1630 def __init__(self
, pspec
):
1631 self
.ti
= TestIssuerInternal(pspec
)
1632 self
.pll
= DummyPLL(instance
=True)
1634 self
.dbg_rst_i
= Signal(reset_less
=True)
1636 # PLL direct clock or not
1637 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1639 self
.pll_test_o
= Signal(reset_less
=True)
1640 self
.pll_vco_o
= Signal(reset_less
=True)
1641 self
.clk_sel_i
= Signal(2, reset_less
=True)
1642 self
.ref_clk
= ClockSignal() # can't rename it but that's ok
1643 self
.pllclk_clk
= ClockSignal("pllclk")
1645 def elaborate(self
, platform
):
1649 # TestIssuer nominally runs at main clock, actually it is
1650 # all combinatorial internally except for coresync'd components
1651 m
.submodules
.ti
= ti
= self
.ti
1654 # ClockSelect runs at PLL output internal clock rate
1655 m
.submodules
.wrappll
= pll
= self
.pll
1657 # add clock domains from PLL
1658 cd_pll
= ClockDomain("pllclk")
1661 # PLL clock established. has the side-effect of running clklsel
1662 # at the PLL's speed (see DomainRenamer("pllclk") above)
1663 pllclk
= self
.pllclk_clk
1664 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1666 # wire up external 24mhz to PLL
1667 #comb += pll.clk_24_i.eq(self.ref_clk)
1668 # output 18 mhz PLL test signal, and analog oscillator out
1669 comb
+= self
.pll_test_o
.eq(pll
.pll_test_o
)
1670 comb
+= self
.pll_vco_o
.eq(pll
.pll_vco_o
)
1672 # input to pll clock selection
1673 comb
+= pll
.clk_sel_i
.eq(self
.clk_sel_i
)
1675 # now wire up ResetSignals. don't mind them being in this domain
1676 pll_rst
= ResetSignal("pllclk")
1677 comb
+= pll_rst
.eq(ResetSignal())
1679 # internal clock is set to selector clock-out. has the side-effect of
1680 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1681 # debug clock runs at coresync internal clock
1682 if self
.ti
.dbg_domain
!= 'sync':
1683 cd_dbgsync
= ClockDomain("dbgsync")
1684 intclk
= ClockSignal(self
.ti
.core_domain
)
1685 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1686 # XXX BYPASS PLL XXX
1687 # XXX BYPASS PLL XXX
1688 # XXX BYPASS PLL XXX
1690 comb
+= intclk
.eq(self
.ref_clk
)
1691 assert self
.ti
.core_domain
!= 'sync', \
1692 "cannot set core_domain to sync and use pll at the same time"
1694 if self
.ti
.core_domain
!= 'sync':
1695 comb
+= intclk
.eq(ClockSignal())
1696 if self
.ti
.dbg_domain
!= 'sync':
1697 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1698 comb
+= dbgclk
.eq(intclk
)
1699 comb
+= self
.ti
.dbg_rst_i
.eq(self
.dbg_rst_i
)
1704 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1705 [ClockSignal(), ResetSignal()]
1707 def external_ports(self
):
1708 ports
= self
.ti
.external_ports()
1709 ports
.append(ClockSignal())
1710 ports
.append(ResetSignal())
1712 ports
.append(self
.clk_sel_i
)
1713 ports
.append(self
.pll
.clk_24_i
)
1714 ports
.append(self
.pll_test_o
)
1715 ports
.append(self
.pll_vco_o
)
1716 ports
.append(self
.pllclk_clk
)
1717 ports
.append(self
.ref_clk
)
1721 if __name__
== '__main__':
1722 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1728 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1729 imem_ifacetype
='bare_wb',
1734 dut
= TestIssuer(pspec
)
1735 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1737 if len(sys
.argv
) == 1:
1738 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1739 with
open("test_issuer.il", "w") as f
: