src/soc/simple/issuer_verilog.py

   1 """simple core issuer verilog generator
   2 """
   3
   4 import argparse
   5 from nmigen.cli import verilog
   6
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.simple.issuer import TestIssuer
   9
  10
  11 if __name__ == '__main__':
  12     parser = argparse.ArgumentParser(description="Simple core issuer " \
  13                                      "verilog generator")
  14     parser.add_argument("output_filename")
  15     parser.add_argument("--enable-xics", action="store_true",
  16                         help="Enable interrupts",
  17                         default=True)
  18     parser.add_argument("--enable-core", action="store_true",
  19                         help="Enable main core",
  20                         default=True)
  21     parser.add_argument("--use-pll", action="store_true", help="Enable pll",
  22                         default=False)
  23     parser.add_argument("--enable-testgpio", action="store_true",
  24                         help="Disable gpio pins",
  25                         default=False)
  26     parser.add_argument("--debug", default="jtag", help="Select debug " \
  27                         "interface [jtag | dmi] [default jtag]")
  28
  29     args = parser.parse_args()
  30
  31     print(args)
  32
  33     units = {'alu': 1,
  34              'cr': 1, 'branch': 1, 'trap': 1,
  35              'logical': 1,
  36              'spr': 1,
  37              'div': 1,
  38              'mul': 1,
  39              'shiftrot': 1
  40             }
  41     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
  42                          imem_ifacetype='bare_wb',
  43                          addr_wid=48,
  44                          mask_wid=8,
  45                          # must leave at 64
  46                          reg_wid=64,
  47                          # set to 32 for instruction-memory width=32
  48                          imem_reg_wid=64,
  49                          # set to 32 to make data wishbone bus 32-bit
  50                          #wb_data_wid=32,
  51                          xics=args.enable_xics, # XICS interrupt controller
  52                          nocore=not args.enable_core, # test coriolis2 ioring
  53                          use_pll=args.use_pll,  # bypass PLL
  54                          gpio=args.enable_testgpio, # for test purposes
  55                          debug=args.debug,      # set to jtag or dmi
  56                          units=units)
  57
  58     dut = TestIssuer(pspec)
  59
  60     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
  61     with open(args.output_filename, "w") as f:
  62         f.write(vl)