Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / Makefile

diff --git a/Makefile b/Makefile
index abb446dd00b02008e36f3412235f37be5194d312..15670cf8b3babf7f8e0991cd3e5100fecb68d273 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -11,13 +11,15 @@ mkpinmux:
        cp pinmux/ls180/ls180_pins.py src/soc/debug
        cp pinmux/ls180/ls180_pins.py src/soc/litex/florent/libresoc
 
-install: gitupdate develop mkpinmux svanalysis
+install: gitupdate develop mkpinmux
 
+# this is now actually part of openpower-isa repository
 pywriter:
-       python3 src/soc/decoder/pseudo/pywriter.py
+       echo "pywriter is part of openpower-isa, run that instead"
 
+# this is now actually part of openpower-isa repository
 svanalysis:
-       python3 libreriscv/openpower/sv_analysis.py
+       echo "sv_analysis is part of openpower-isa, run that instead"
 
 develop:
        python3 setup.py develop # yes, develop, not install
@@ -36,6 +38,12 @@ testgpio_run_sim:
        python3 src/soc/litex/florent/sim.py --cpu=libresoc \
                        --variant=standardjtagtestgpio
 
+ls180_verilog_nopll:
+       python3 src/soc/simple/issuer_verilog.py \
+               --debug=jtag --enable-core --disable-pll \
+               --enable-xics --disable-svp64 \
+                       src/soc/litex/florent/libresoc/libresoc.v
+
 ls180_verilog:
        python3 src/soc/simple/issuer_verilog.py \
                --debug=jtag --enable-core --enable-pll \
@@ -48,6 +56,43 @@ ls180_4k_verilog:
                --enable-xics --enable-sram4x4kblock --disable-svp64 \
                        src/soc/litex/florent/libresoc/libresoc.v
 
+# build microwatt "external core", note that the TLB set size is set to 16
+# for I/D-Cache which needs a corresponding alteration of the device-tree
+# entries for linux
+microwatt_external_core:
+       python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \
+            external_core_top.v
+
+# build microwatt "external core" with fixed 64-bit width SVP64
+# note that the TLB set size is set to 16
+# for I/D-Cache which needs a corresponding alteration of the device-tree
+# entries for linux
+microwatt_external_core_svp64:
+       python3 src/soc/simple/issuer_verilog.py --microwatt-compat-svp64 --enable-mmu \
+            external_core_top.v
+
+microwatt_external_core_spi:
+       python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+            --small-cache \
+            --enable-mmu \
+            --pc-reset 0x10000000 \
+            external_core_top.v
+
+# microwatt-compatible core with smaller cache size (quick. VERSA_ECP5. just)
+microwatt_external_core_bram:
+       python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+            --small-cache \
+            --enable-mmu \
+            --pc-reset 0xFF000000 \
+            external_core_top.v
+
+# microwatt-compatible core with larger cache size (experiment on arty)
+microwatt_external_core_bram_arty:
+       python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+            --enable-mmu \
+            --pc-reset 0xFF000000 \
+            external_core_top.v
+
 # build the litex libresoc SoC without 4k SRAMs
 ls180_verilog_build: ls180_verilog
        make -C soc/soc/litex/florent ls180
@@ -60,6 +105,9 @@ ls180_4ksram_verilog_build: ls180_4k_verilog
 test: install
        python3 setup.py test # could just run nosetest3...
 
+pypiupload:
+       $(PYTHON3) setup.py sdist upload
+
 # Minimal makefile for Sphinx documentation
 #