Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / conf.py

diff --git a/conf.py b/conf.py
index 34d9b3f7ce3ea4c3ef647ba2a6d330a29609cd83..d752f59ef042ac4b8d5f42bcebdf50308f0ee585 100644 (file)
--- a/conf.py
+++ b/conf.py
@@ -47,7 +47,7 @@ extensions = [
     'sphinx.ext.coverage',
     'recommonmark',
     #'symbolator_sphinx',
-    'sphinxcontrib_verilog_diagrams',
+    #'sphinxcontrib_verilog_diagrams', # XXX now spinxcontrib-hdl-diagrams
     'sphinx_rtd_theme',
     #'sphinx_tabs.tabs',
 ]
@@ -179,8 +179,8 @@ lsocbase = 'https://docs.libre-soc.org/'
 intersphinx_mapping = {"python": ('https://docs.python.org/3', None),
                        "nmigen": ('https://nmigen.info/nmigen', 'latest'),
                        "openpower": (lsocbase+'openpower-isa', None),
-                       "nmutil": (lsocbase+'nmutil', None),
-                       "ieee754fpu": (lsocbase+'ieee754fpu', None),
+                       #"nmutil": (lsocbase+'nmutil', None),
+                       #"ieee754fpu": (lsocbase+'ieee754fpu', None),
                       }
 
 # -- Options for todo extension ----------------------------------------------