partial Unit Test for TLB

[soc.git] / src / TLB / TLB.py

diff --git a/src/TLB/TLB.py b/src/TLB/TLB.py
index 3538bdc1dcab904c0ea803fac903493939007852..98c9af72bc0a9153757ce66cc1360bfe43f021d8 100644 (file)
--- a/src/TLB/TLB.py
+++ b/src/TLB/TLB.py
@@ -5,13 +5,13 @@
     * Tag (N - 79) / ASID (78 - 64) / PTE (63 - 0)
 """
 
-from nmigen import Memory, Module, Signal, Cat
+from nmigen import Memory, Module, Signal, Cat, Elaboratable
 from nmigen.cli import main
 
-from PermissionValidator import PermissionValidator
-from Cam import Cam
+from .PermissionValidator import PermissionValidator
+from .Cam import Cam
 
-class TLB():
+class TLB(Elaboratable):
     def __init__(self, asid_size, vma_size, pte_size, L1_size):
         """ Arguments
             * asid_size: Address Space IDentifier (ASID) typically 15 bits
@@ -27,7 +27,6 @@ class TLB():
         # Internal
         self.state = 0
         # L1 Cache Modules
-        L1_size = 8 # XXX overridden incoming argument?
         self.cam_L1 = Cam(vma_size, L1_size)
         self.mem_L1 = Memory(asid_size + pte_size, L1_size)
 
@@ -117,18 +116,21 @@ class TLB():
         # CAM_L1 Logic
         m.d.comb += [
             self.cam_L1.write_enable.eq(1),
-            self.cam_L1.data_in.eq(self.vma),
+            self.cam_L1.data_in.eq(self.vma), #data_in is sent to all entries
+            # self.cam_L1.address_in.eq(todo) # a CAM entry needs to be selected
+            
         ]
 
     def elaborate(self, platform):
         m = Module()
         # Add submodules
         # Submodules for L1 Cache
-        m.d.submodules.cam_L1 = self.cam_L1
-        m.d.sumbmodules.read_L1 = read_L1 = self.mem_L1.read_port()
-        m.d.sumbmodules.read_L1 = write_L1 = self.mem_L1.write_port()
+        m.submodules.cam_L1 = self.cam_L1
+        m.submodules.read_L1 = read_L1 = self.mem_L1.read_port()
+        m.submodules.write_L1 = write_L1 = self.mem_L1.write_port()
+        
         # Permission Validator Submodule
-        m.d.submodules.perm_valididator = self.perm_validator
+        m.submodules.perm_valididator = self.perm_validator
 
         # When MODE specifies translation
         # TODO add in different bit length handling ie prefix 0s