add is_512G to the data structure

[soc.git] / src / TLB / ariane / tlb.py

diff --git a/src/TLB/ariane/tlb.py b/src/TLB/ariane/tlb.py
index f768571ed28377e3fad3f5c30615e3f1842e4035..cf4af57adfecc15d28e0facf9ab6dbbe7b285e85 100644 (file)
--- a/src/TLB/ariane/tlb.py
+++ b/src/TLB/ariane/tlb.py
@@ -12,7 +12,7 @@
 # Author: David Schaffenrath, TU Graz
 # Author: Florian Zaruba, ETH Zurich
 # Date: 21.4.2017
-# Description: Translation Lookaside Buffer, SV39
+# Description: Translation Lookaside Buffer, SV48
 #              fully set-associative
 
 Implementation in c++:
@@ -25,17 +25,17 @@ Online simulator:
 http://www.ntu.edu.sg/home/smitha/ParaCache/Paracache/vm.html
 """
 from math import log2
-from nmigen import Signal, Module, Cat, Const, Array
+from nmigen import Signal, Module, Cat, Const, Array, Elaboratable
 from nmigen.cli import verilog, rtlil
 from nmigen.lib.coding import Encoder
 
-from ptw import TLBUpdate, PTE, ASID_WIDTH
-from plru import PLRU
-from tlb_content import TLBContent
+from TLB.ariane.ptw import TLBUpdate, PTE, ASID_WIDTH
+from TLB.ariane.plru import PLRU
+from TLB.ariane.tlb_content import TLBContent
 
 TLB_ENTRIES = 8
 
-class TLB:
+class TLB(Elaboratable):
     def __init__(self, tlb_entries=8, asid_width=8):
         self.tlb_entries = tlb_entries
         self.asid_width = asid_width
@@ -48,6 +48,7 @@ class TLB:
         self.lu_content_o = PTE()
         self.lu_is_2M_o = Signal()
         self.lu_is_1G_o = Signal()
+        self.lu_is_512G_o = Signal()
         self.lu_hit_o = Signal()
         # Update TLB
         self.pte_width = len(self.lu_content_o.flatten())
@@ -56,6 +57,7 @@ class TLB:
     def elaborate(self, platform):
         m = Module()
 
+        vpn3 = Signal(9) #FIXME unused signal
         vpn2 = Signal(9)
         vpn1 = Signal(9)
         vpn0 = Signal(9)
@@ -64,10 +66,11 @@ class TLB:
         # Translation
         #-------------
 
-        # SV39 defines three levels of page tables
+        # SV48 defines four levels of page tables
         m.d.comb += [ vpn0.eq(self.lu_vaddr_i[12:21]),
                       vpn1.eq(self.lu_vaddr_i[21:30]),
                       vpn2.eq(self.lu_vaddr_i[30:39]),
+                      vpn3.eq(self.lu_vaddr_i[39:48]),      ### FIXME
                     ]
 
         tc = []
@@ -80,6 +83,7 @@ class TLB:
             m.d.comb += [tlc.vpn0.eq(vpn0),
                          tlc.vpn1.eq(vpn1),
                          tlc.vpn2.eq(vpn2),
+                         # TODO 4th
                          tlc.flush_i.eq(self.flush_i),
                          #tlc.update_i.eq(self.update_i),
                          tlc.lu_asid_i.eq(self.lu_asid_i)]
@@ -104,7 +108,8 @@ class TLB:
         m.d.comb += active.eq(~hitsel.n)
         with m.If(active):
             # active hit, send selected as output
-            m.d.comb += [ self.lu_is_1G_o.eq(tc[idx].lu_is_1G_o),
+            m.d.comb += [ self.lu_is_512G_o.eq(tc[idx].lu_is_512G_o),
+                          self.lu_is_1G_o.eq(tc[idx].lu_is_1G_o),
                           self.lu_is_2M_o.eq(tc[idx].lu_is_2M_o),
                           self.lu_hit_o.eq(1),
                           self.lu_content_o.flatten().eq(tc[idx].lu_content_o),
@@ -159,7 +164,7 @@ class TLB:
     def ports(self):
         return [self.flush_i, self.lu_access_i,
                  self.lu_asid_i, self.lu_vaddr_i,
-                 self.lu_is_2M_o, self.lu_is_1G_o, self.lu_hit_o,
+                 self.lu_is_2M_o, self.lu_1G_o, self.lu_is_512G_o, self.lu_hit_o
                 ] + self.lu_content_o.ports() + self.update_i.ports()
 
 if __name__ == '__main__':