whoops forgot to make CU decisions based on latched opcode

[soc.git] / src / experiment / compalu.py

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index 12e519f0631b3b498240497a530441d51240c49c..1735e24cf09e6fc2a273fcf139b0feed99f6e101 100644 (file)
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -51,6 +51,7 @@ class ComputationUnitNoDelay(Elaboratable):
         self.go_die_i = Signal() # go die (reset)
 
         self.oper_i = Signal(opwid, reset_less=True) # opcode in
+        self.imm_i = Signal(rwid, reset_less=True) # immediate in
         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
         self.src2_i = Signal(rwid, reset_less=True) # oper2 in
 
@@ -93,19 +94,20 @@ class ComputationUnitNoDelay(Elaboratable):
         # XXX
 
         # outputs
-        m.d.comb += self.busy_o.eq(opc_l.q) # busy out
-        m.d.comb += self.rd_rel_o.eq(src_l.q & opc_l.q) # src1/src2 req rel
+        busy_o = self.busy_o
+        m.d.comb += busy_o.eq(opc_l.q) # busy out
+        m.d.comb += self.rd_rel_o.eq(src_l.q & busy_o) # src1/src2 req rel
 
         # the counter is just for demo purposes, to get the ALUs of different
         # types to take arbitrary completion times
         with m.If(opc_l.qn):
             m.d.sync += self.counter.eq(0)
-        with m.If(req_l.qn & opc_l.q & (self.counter == 0)):
-            with m.If(self.oper_i == 2): # MUL, to take 5 instructions
+        with m.If(req_l.qn & busy_o & (self.counter == 0)):
+            with m.If(self.alu.op == 2): # MUL, to take 5 instructions
                 m.d.sync += self.counter.eq(5)
-            with m.Elif(self.oper_i == 3): # SHIFT to take 7
+            with m.Elif(self.alu.op == 3): # SHIFT to take 7
                 m.d.sync += self.counter.eq(7)
-            with m.Elif(self.counter >= 4): # Branches take 6 (to test shadow)
+            with m.Elif(self.alu.op >= 4): # Branches take 6 (to test shadow)
                 m.d.sync += self.counter.eq(6)
             with m.Else(): # ADD/SUB to take 2
                 m.d.sync += self.counter.eq(2)
@@ -113,7 +115,7 @@ class ComputationUnitNoDelay(Elaboratable):
             m.d.sync += self.counter.eq(self.counter - 1)
         with m.If(self.counter == 1):
             # write req release out.  waits until shadow is dropped.
-            m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q & self.shadown_i)
+            m.d.comb += self.req_rel_o.eq(req_l.q & busy_o & self.shadown_i)
 
         # create a latch/register for src1/src2
         latchregister(m, self.src1_i, self.alu.a, src_l.q)
@@ -122,7 +124,7 @@ class ComputationUnitNoDelay(Elaboratable):
         #    m.d.comb += self.alu.op.eq(self.oper_i)
 
         # create a latch/register for the operand
-        latchregister(m, self.oper_i, self.alu.op, src_l.q)
+        latchregister(m, self.oper_i, self.alu.op, self.issue_i)
 
         # and one for the output from the ALU
         data_r = Signal(self.rwid, reset_less=True) # Dest register