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add address and output mode from LDSTCUs
[soc.git]
/
src
/
experiment
/
compldst.py
diff --git
a/src/experiment/compldst.py
b/src/experiment/compldst.py
index 0a0a4c2ee462613ad2f7974d688224a26463638c..e2fccf87e393e598ccd00a4bd14396b05b17a6ad 100644
(file)
--- a/
src/experiment/compldst.py
+++ b/
src/experiment/compldst.py
@@
-78,6
+78,7
@@
class LDSTCompUnit(Elaboratable):
self.sto_rel_o = Signal(reset_less=True) # request store (to mem)
self.req_rel_o = Signal(reset_less=True) # request write (result)
self.data_o = Signal(rwid, reset_less=True) # Dest out (LD or ALU)
self.sto_rel_o = Signal(reset_less=True) # request store (to mem)
self.req_rel_o = Signal(reset_less=True) # request write (result)
self.data_o = Signal(rwid, reset_less=True) # Dest out (LD or ALU)
+ self.addr_o = Signal(rwid, reset_less=True) # Address out (LD or ST)
# hmm... TODO... move these to outside of LDSTCompUnit
self.load_mem_o = Signal(reset_less=True) # activate memory LOAD
# hmm... TODO... move these to outside of LDSTCompUnit
self.load_mem_o = Signal(reset_less=True) # activate memory LOAD
@@
-214,7
+215,12
@@
class LDSTCompUnit(Elaboratable):
m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
# put the register directly onto the output
m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
# put the register directly onto the output
- comb += self.data_o.eq(data_r)
+ with m.If((self.go_wr_i & ~op_ldst) | (self.go_st_i & op_is_st)):
+ comb += self.data_o.eq(data_r)
+
+ # put the register directly onto the address bus
+ with m.If(self.go_ad_i):
+ comb += self.addr_o.eq(data_r)
return m
return m