self.go_die_i = Signal(n_units, reset_less=True)
if ldstmode:
self.go_ad_i = Signal(n_units, reset_less=True)
+ self.go_st_i = Signal(n_units, reset_less=True)
# outputs
self.busy_o = Signal(n_units, reset_less=True)
self.rd_rel_o = Signal(n_units, reset_less=True)
self.req_rel_o = Signal(n_units, reset_less=True)
if ldstmode:
+ self.ld_o = Signal(n_units, reset_less=True) # op is LD
+ self.st_o = Signal(n_units, reset_less=True) # op is ST
self.adr_rel_o = Signal(n_units, reset_less=True)
self.sto_rel_o = Signal(n_units, reset_less=True)
self.req_rel_o = Signal(n_units, reset_less=True)
ldmem_l = []
stmem_l = []
go_ad_l = []
+ go_st_l = []
+ ld_l = []
+ st_l = []
adr_rel_l = []
sto_rel_l = []
for alu in self.units:
+ ld_l.append(alu.ld_o)
+ st_l.append(alu.st_o)
adr_rel_l.append(alu.adr_rel_o)
sto_rel_l.append(alu.sto_rel_o)
ldmem_l.append(alu.load_mem_o)
stmem_l.append(alu.stwd_mem_o)
go_ad_l.append(alu.go_ad_i)
+ go_st_l.append(alu.go_st_i)
comb += self.adr_rel_o.eq(Cat(*adr_rel_l))
comb += self.sto_rel_o.eq(Cat(*sto_rel_l))
comb += self.load_mem_o.eq(Cat(*ldmem_l))
comb += self.stwd_mem_o.eq(Cat(*stmem_l))
comb += Cat(*go_ad_l).eq(self.go_ad_i)
+ comb += Cat(*go_st_l).eq(self.go_st_i)
return m
class CompUnitLDSTs(CompUnitsBase):
- def __init__(self, rwid, opwid, mem):
+ def __init__(self, rwid, opwid, n_ldsts, mem):
""" Inputs:
* :rwid: bit width of register file(s) - both FP and INT
self.imm_i = Signal(rwid, reset_less=True)
# Int ALUs
- add1 = ALU(rwid)
- add2 = ALU(rwid)
+ self.alus = []
+ for i in range(n_ldsts):
+ self.alus.append(ALU(rwid))
units = []
- for alu in [add1, add2]:
+ for alu in self.alus:
aluopwid = 4 # see compldst.py for "internal" opcode
units.append(LDSTCompUnit(rwid, aluopwid, alu, mem))
self.fpregs = RegFileArray(rwid, n_regs)
# issue q needs to get at these
- self.aluissue = IssueUnitGroup(4)
+ self.aluissue = IssueUnitGroup(2)
+ self.lsissue = IssueUnitGroup(2)
self.brissue = IssueUnitGroup(1)
- self.lsissue = IssueUnitGroup(1)
# and these
self.alu_oper_i = Signal(4, reset_less=True)
self.alu_imm_i = Signal(rwid, reset_less=True)
# Int ALUs and BR ALUs
n_int_alus = 5
- cua = CompUnitALUs(self.rwid, 3, n_alus=4)
+ cua = CompUnitALUs(self.rwid, 3, n_alus=self.aluissue.n_insns)
cub = CompUnitBR(self.rwid, 3) # 1 BR ALUs
# LDST Comp Units
n_ldsts = 2
- cul = CompUnitLDSTs(self.rwid, 4, None)
+ cul = CompUnitLDSTs(self.rwid, 4, self.lsissue.n_insns, None)
# Comp Units
- m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub, cul])
+ m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cul, cub])
bgt = cub.bgt # get at the branch computation unit
br1 = cub.br1
# INT/FP Issue Unit
regdecode = RegDecode(self.n_regs)
m.submodules.regdecode = regdecode
- issueunit = IssueUnitArray([self.aluissue, self.brissue, self.lsissue])
+ issueunit = IssueUnitArray([self.aluissue, self.lsissue, self.brissue])
m.submodules.issueunit = issueunit
# Shadow Matrix. currently n_intfus shadows, to be used for
comb += issueunit.busy_i.eq(cu.busy_o)
comb += self.busy_o.eq(cu.busy_o.bool())
+ #---------
+ # Memory Function Unit
+ #---------
+ reset_b = Signal(cul.n_units, reset_less=True)
+ sync += reset_b.eq(cul.go_st_i | cul.go_wr_i | cul.go_die_i)
+
+
+ comb += memfus.fn_issue_i.eq(cul.issue_i) # Comp Unit Issue -> Mem FUs
+ comb += memfus.addr_en_i.eq(cul.adr_rel_o) # Match enable on adr rel
+ comb += memfus.addr_rs_i.eq(reset_b) # reset same as LDSTCompUnit
+
+ # LD/STs have to accumulate prior LD/STs (TODO: multi-issue as well,
+ # in a transitive fashion). This cycle activates based on LDSTCompUnit
+ # issue_i. multi-issue gets a bit more complex but not a lot.
+ prior_ldsts = Signal(cul.n_units, reset_less=True)
+ sync += prior_ldsts.eq(memfus.g_int_ld_pend_o | memfus.g_int_st_pend_o)
+ with m.If(self.ls_oper_i[2]): # LD bit of operand
+ comb += memfus.ld_i.eq(cul.issue_i | prior_ldsts)
+ with m.If(self.ls_oper_i[3]): # ST bit of operand
+ comb += memfus.st_i.eq(cul.issue_i | prior_ldsts)
+
+ # TODO: adr_rel_o needs to go into L1 Cache. for now,
+ # just immediately activate go_adr
+ comb += cul.go_ad_i.eq(cul.adr_rel_o)
+
+ # connect up address data
+ comb += memfus.addrs_i[0].eq(cul.units[0].data_o)
+ comb += memfus.addrs_i[1].eq(cul.units[1].data_o)
+
+ # connect loadable / storable to go_ld/go_st.
+ # XXX should only be done when the memory ld/st has actually happened!
+ go_st_i = Signal(cul.n_units, reset_less=True)
+ go_ld_i = Signal(cul.n_units, reset_less=True)
+ comb += go_ld_i.eq(memfus.storable_o & memfus.addr_nomatch_o &\
+ cul.req_rel_o & cul.ld_o)
+ comb += go_st_i.eq(memfus.storable_o & memfus.addr_nomatch_o &\
+ cul.sto_rel_o & cul.st_o)
+ comb += memfus.go_ld_i.eq(go_ld_i)
+ comb += memfus.go_st_i.eq(go_st_i)
+ #comb += cul.go_wr_i.eq(memfus.loadable_o & memfus.addr_nomatch_o)
+ comb += cul.go_st_i.eq(go_st_i)
+
+ #comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus])
+ #comb += cu.go_wr_i[0:n_intfus].eq(go_wr_o[0:n_intfus])
+ #comb += cu.issue_i[0:n_intfus].eq(fn_issue_o[0:n_intfus])
+
#---------
# merge shadow matrices outputs
#---------
# ok connect first n_int_fu shadows to busy lines, to create an
# instruction-order linked-list-like arrangement, using a bit-matrix
# (instead of e.g. a ring buffer).
- # XXX TODO
# when written, the shadow can be cancelled (and was good)
for i in range(n_intfus):
with m.If(br1.issue_i):
sync += bspec.active_i.eq(1)
with m.If(self.branch_succ_i):
- comb += bspec.good_i.eq(fn_issue_o & 0x1f)
+ comb += bspec.good_i.eq(fn_issue_o & 0x1f) # XXX MAGIC CONSTANT
with m.If(self.branch_fail_i):
- comb += bspec.fail_i.eq(fn_issue_o & 0x1f)
+ comb += bspec.fail_i.eq(fn_issue_o & 0x1f) # XXX MAGIC CONSTANT
# branch is active (TODO: a better signal: this is over-using the
# go_write signal - actually the branch should not be "writing")
if False:
instrs = create_random_ops(dut, 15, True, 4)
- if True: # LD test (with immediate)
- instrs.append( (1, 2, 2, 0x20, 1, 20, (0, 0)) )
+ if True: # LD/ST test (with immediate)
+ instrs.append( (1, 2, 2, 0x10, 1, 1, (0, 0)) )
+ instrs.append( (1, 2, 7, 0x12, 1, 1, (0, 0)) )
if False:
instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )
projects / soc.git / blobdiff