# inputs
self.oper_i = Signal(opwid, reset_less=True)
+ self.imm_i = Signal(rwid, reset_less=True)
# Branch ALU and CU
self.bgt = BranchALU(rwid)
- self.br1 = ComputationUnitNoDelay(rwid, 3, self.bgt)
+ aluopwid = 3 # extra bit for immediate mode
+ self.br1 = ComputationUnitNoDelay(rwid, aluopwid, self.bgt)
CompUnitsBase.__init__(self, rwid, [self.br1])
def elaborate(self, platform):
# hand the same operation to all units
for alu in self.units:
comb += alu.oper_i.eq(self.oper_i)
+ comb += alu.imm_i.eq(self.imm_i)
return m
intregdeps = FURegDepMatrix(n_intfus, self.n_regs)
m.submodules.intregdeps = intregdeps
- comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o)
- comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o)
+ comb += self.g_int_rd_pend_o.eq(intregdeps.v_rd_rsel_o)
+ comb += self.g_int_wr_pend_o.eq(intregdeps.v_wr_rsel_o)
- comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o)
- comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o)
+ comb += intregdeps.rd_pend_i.eq(intregdeps.v_rd_rsel_o)
+ comb += intregdeps.wr_pend_i.eq(intregdeps.v_wr_rsel_o)
comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o)
comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o)
self.alu_oper_i = Signal(4, reset_less=True)
self.alu_imm_i = Signal(rwid, reset_less=True)
self.br_oper_i = Signal(4, reset_less=True)
+ self.br_imm_i = Signal(rwid, reset_less=True)
# inputs
self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
# Int ALUs and Comp Units
n_int_alus = 5
cua = CompUnitALUs(self.rwid, 3)
- cub = CompUnitBR(self.rwid, 2)
+ cub = CompUnitBR(self.rwid, 3)
m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub])
bgt = cub.bgt # get at the branch computation unit
br1 = cub.br1
comb += cua.oper_i.eq(self.alu_oper_i)
comb += cua.imm_i.eq(self.alu_imm_i)
comb += cub.oper_i.eq(self.br_oper_i)
+ comb += cub.imm_i.eq(self.br_imm_i)
# TODO: issueunit.f (FP)
# choose a Function-Unit-Group
with m.If((op & (0x3<<2)) != 0): # branch
comb += sc.brissue.insn_i.eq(1)
- comb += sc.br_oper_i.eq(op & 0x3)
+ comb += sc.br_oper_i.eq(Cat(op[0:2], opi))
+ comb += sc.br_imm_i.eq(imm)
comb += wait_issue_br.eq(1)
with m.Else(): # alu
comb += sc.aluissue.insn_i.eq(1)
if (op & (0x3<<2)) != 0: # branch
yield dut.brissue.insn_i.eq(1)
yield dut.br_oper_i.eq(Const(op & 0x3, 2))
+ yield dut.br_imm_i.eq(imm)
dut_issue = dut.brissue
else:
yield dut.aluissue.insn_i.eq(1)
seed(0)
- for i in range(1):
+ for i in range(50):
# set random values in the registers
for i in range(1, dut.n_regs):
# create some instructions (some random, some regression tests)
instrs = []
- if False:
+ if True:
instrs = create_random_ops(dut, 15, True, 4)
if False:
instrs.append((5, 3, 3, 3, 0, 0, (0, 0)))
instrs.append((3, 5, 5, 0, 0, 0, (0, 0)))
- if True:
+ if False:
instrs.append( (3, 3, 4, 0, 0, 13979, (0, 0)))
instrs.append( (6, 4, 1, 2, 0, 40976, (0, 0)))
instrs.append( (1, 4, 7, 4, 1, 23652, (0, 0)))