from math import log
+class Memory(Elaboratable):
+ def __init__(self, regwid, addrw):
+ self.ddepth = regwid/8
+ depth = (1<<addrw) / self.ddepth
+ self.adr = Signal(addrw)
+ self.dat_r = Signal(regwid)
+ self.dat_w = Signal(regwid)
+ self.we = Signal()
+ self.mem = Memory(width=regwid, depth=depth, init=range(0, depth))
+
+ def elaborate(self, platform):
+ m = Module()
+ m.submodules.rdport = rdport = self.mem.read_port()
+ m.submodules.wrport = wrport = self.mem.write_port()
+ m.d.comb += [
+ rdport.addr.eq(self.adr[self.ddepth:]), # ignore low bits
+ self.dat_r.eq(rdport.data),
+ wrport.addr.eq(self.adr),
+ wrport.data.eq(self.dat_w),
+ wrport.en.eq(self.we),
+ ]
+ return m
+
+
+class MemSim:
+ def __init__(self, regwid, addrw):
+ self.regwid = regwid
+ self.ddepth = regwid//8
+ depth = (1<<addrw) // self.ddepth
+ self.mem = list(range(0, depth))
+
+ def ld(self, addr):
+ return self.mem[addr>>self.ddepth]
+
+ def st(self, addr, data):
+ self.mem[addr>>self.ddepth] = data & ((1<<self.regwid)-1)
+
+
class CompUnitsBase(Elaboratable):
""" Computation Unit Base class.
# hand the same operation to all units
for alu in self.units:
comb += alu.oper_i.eq(self.oper_i)
- #comb += self.units[0].oper_i.eq(Const(0, 2)) # op=add
- #comb += self.units[1].oper_i.eq(Const(1, 2)) # op=sub
- #comb += self.units[2].oper_i.eq(Const(2, 2)) # op=mul
- #comb += self.units[3].oper_i.eq(Const(3, 2)) # op=shf
return m
# hand the same operation to all units
for alu in self.units:
comb += alu.oper_i.eq(self.oper_i)
- #comb += self.br1.oper_i.eq(Const(4, 3)) # op=bgt
return m
m.submodules.bshadow = bshadow = ShadowMatrix(n_intfus, 1, False)
# record previous instruction to cast shadow on current instruction
- fn_issue_prev = Signal(n_intfus)
prev_shadow = Signal(n_intfus)
# Branch Speculation recorder. tracks the success/fail state as
for i in range(n_intfus):
comb += shadows.s_good_i[i][0:n_intfus].eq(go_wr_o[0:n_intfus])
- # work out the current-activated busy unit (by recording the old one)
- with m.If(fn_issue_o): # only update prev bit if instruction issued
- sync += fn_issue_prev.eq(fn_issue_o)
-
# *previous* instruction shadows *current* instruction, and, obviously,
# if the previous is completed (!busy) don't cast the shadow!
comb += prev_shadow.eq(~fn_issue_o & cu.busy_o)
def ports(self):
return list(self)
+
class IssueToScoreboard(Elaboratable):
def __init__(self, qlen, n_in, n_out, rwid, opwid, n_regs):
def ports(self):
return list(self)
+
IADD = 0
ISUB = 1
IMUL = 2
self.rwidth = rwidth
self.regs = [0] * nregs
- def op(self, op, src1, src2, dest):
+ def op(self, op, op_imm, src1, src2, dest):
maxbits = (1 << self.rwidth) - 1
src1 = self.regs[src1] & maxbits
- src2 = self.regs[src2] & maxbits
+ if not op_imm: # put op in src2
+ src2 = self.regs[src2] & maxbits
if op == IADD:
val = src1 + src2
elif op == ISUB:
yield from self.dump(dut)
assert False
-def instr_q(dut, op, src1, src2, dest, branch_success, branch_fail):
- instrs = [{'oper_i': op, 'dest_i': dest, 'src1_i': src1, 'src2_i': src2}]
+def instr_q(dut, op, op_imm, src1, src2, dest, branch_success, branch_fail):
+ instrs = [{'oper_i': op, 'dest_i': dest, 'opim_i': op_imm,
+ 'src1_i': src1, 'src2_i': src2}]
sendlen = 1
for idx in range(sendlen):
src2 = randint(1, dut.n_regs-1)
dest = randint(1, dut.n_regs-1)
op = randint(0, max_opnums)
+ opi = 0 if randint(0, 3) else 1 # set true if random is nonzero
if shadowing:
- insts.append((src1, src2, dest, op, (0, 0)))
+ insts.append((src1, src2, dest, op, opi, (0, 0)))
else:
- insts.append((src1, src2, dest, op))
+ insts.append((src1, src2, dest, op, opi))
return insts
instrs.append((4, 2, 1, 2, (1, 0)))
if False:
- instrs.append( (4, 3, 5, 1, (0, 0)) )
- instrs.append( (5, 2, 3, 1, (0, 0)) )
- instrs.append( (7, 1, 5, 2, (0, 0)) )
- instrs.append( (5, 6, 6, 4, (0, 0)) )
- instrs.append( (7, 5, 2, 2, (1, 0)) )
- instrs.append( (1, 7, 5, 0, (0, 1)) )
- instrs.append( (1, 6, 1, 2, (1, 0)) )
- instrs.append( (1, 6, 7, 3, (0, 0)) )
- instrs.append( (6, 7, 7, 0, (0, 0)) )
+ instrs.append( (4, 3, 5, 1, 0, (0, 0)) )
+ instrs.append( (5, 2, 3, 1, 0, (0, 0)) )
+ instrs.append( (7, 1, 5, 2, 0, (0, 0)) )
+ instrs.append( (5, 6, 6, 4, 0, (0, 0)) )
+ instrs.append( (7, 5, 2, 2, 0, (1, 0)) )
+ instrs.append( (1, 7, 5, 0, 0, (0, 1)) )
+ instrs.append( (1, 6, 1, 2, 0, (1, 0)) )
+ instrs.append( (1, 6, 7, 3, 0, (0, 0)) )
+ instrs.append( (6, 7, 7, 0, 0, (0, 0)) )
# issue instruction(s), wait for issue to be free before proceeding
- for i, (src1, src2, dest, op, (br_ok, br_fail)) in enumerate(instrs):
+ for i, instr in enumerate(instrs):
+ src1, src2, dest, op, opi, (br_ok, br_fail) = instr
print ("instr %d: (%d, %d, %d, %d)" % (i, src1, src2, dest, op))
- alusim.op(op, src1, src2, dest)
- yield from instr_q(dut, op, src1, src2, dest, br_ok, br_fail)
+ alusim.op(op, opi, src1, src2, dest)
+ yield from instr_q(dut, op, opi, src1, src2, dest, br_ok, br_fail)
# wait for all instructions to stop before checking
while True:
def test_scoreboard():
dut = IssueToScoreboard(2, 1, 1, 16, 8, 8)
alusim = RegSim(16, 8)
+ memsim = MemSim(16, 16)
vl = rtlil.convert(dut, ports=dut.ports())
with open("test_scoreboard6600.il", "w") as f:
f.write(vl)
projects / soc.git / blobdiff