# Int ALUs and BR ALUs
n_int_alus = 5
- cua = CompUnitALUs(self.rwid, 3, n_alus=4)
+ cua = CompUnitALUs(self.rwid, 3, n_alus=2)
cub = CompUnitBR(self.rwid, 3) # 1 BR ALUs
# LDST Comp Units
n_ldsts = 2
- cul = CompUnitLDSTs(self.rwid, 3, None)
+ cul = CompUnitLDSTs(self.rwid, 4, None)
# Comp Units
m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub, cul])
with m.If(br1.issue_i):
sync += bspec.active_i.eq(1)
with m.If(self.branch_succ_i):
- comb += bspec.good_i.eq(fn_issue_o & 0x1f)
+ comb += bspec.good_i.eq(fn_issue_o & 0x1f) # XXX MAGIC CONSTANT
with m.If(self.branch_fail_i):
- comb += bspec.fail_i.eq(fn_issue_o & 0x1f)
+ comb += bspec.fail_i.eq(fn_issue_o & 0x1f) # XXX MAGIC CONSTANT
# branch is active (TODO: a better signal: this is over-using the
# go_write signal - actually the branch should not be "writing")
comb += sc.brissue.insn_i.eq(1)
comb += wait_issue_br.eq(1)
with m.Elif((op & (0x3<<4)) != 0): # ld/st
+ # see compldst.py
# bit 0: ADD/SUB
# bit 1: immed
# bit 4: LD
# bit 5: ST
- comb += sc.ls_oper_i.eq(Cat(op[0], opi, op[4:5]))
+ comb += sc.ls_oper_i.eq(Cat(op[0], opi[0], op[4:6]))
comb += sc.ls_imm_i.eq(imm)
comb += sc.lsissue.insn_i.eq(1)
comb += wait_issue_ls.eq(1)
IBEQ = 6
IBNE = 7
+
class RegSim:
def __init__(self, rwidth, nregs):
self.rwidth = rwidth
val = int(src1 == src2)
elif op == IBNE:
val = int(src1 != src2)
+ else:
+ return 0 # LD/ST TODO
val &= maxbits
self.setval(dest, val)
return val
def disable_issue(dut):
yield dut.aluissue.insn_i.eq(0)
yield dut.brissue.insn_i.eq(0)
+ yield dut.lsissue.insn_i.eq(0)
def wait_for_issue(dut, dut_issue):
# create some instructions (some random, some regression tests)
instrs = []
- if True:
+ if False:
instrs = create_random_ops(dut, 15, True, 4)
+ if True: # LD test (with immediate)
+ instrs.append( (1, 2, 2, 0x10, 1, 20, (0, 0)) )
+
if False:
instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )