move FUMemMatchMatrix to mdm module

[soc.git] / src / scoreboard / test_mem2_fu_matrix.py

diff --git a/src/scoreboard/test_mem2_fu_matrix.py b/src/scoreboard/test_mem2_fu_matrix.py
index 80b9e63ffe86eb475de8f97f85667714e0b4aa37..4679105e28519fd465477d769927e9f96fc13b71 100644 (file)
--- a/src/scoreboard/test_mem2_fu_matrix.py
+++ b/src/scoreboard/test_mem2_fu_matrix.py
@@ -4,12 +4,11 @@ from nmigen import Module, Const, Signal, Array, Cat, Elaboratable
 
 from regfile.regfile import RegFileArray, treereduce
 from scoreboard.fu_fu_matrix import FUFUDepMatrix
-from scoreboard.fu_reg_matrix import FURegDepMatrix
 from scoreboard.global_pending import GlobalPending
 from scoreboard.group_picker import GroupPicker
 from scoreboard.issue_unit import IssueUnitGroup, IssueUnitArray, RegDecode
 from scoreboard.shadow import ShadowMatrix, BranchSpeculationRecord
-
+from scoreboard.mdm import FUMemMatchMatrix
 from nmutil.latch import SRLatch
 from nmutil.nmoperator import eq
 
@@ -56,27 +55,35 @@ class MemSim:
         self.mem[addr>>self.ddepth] = data & ((1<<self.regwid)-1)
 
 
+
 class MemFunctionUnits(Elaboratable):
 
-    def __init__(self, n_int_alus):
-        self.n_int_alus = n_int_alus
+    def __init__(self, n_ldsts, addrbitwid):
+        self.n_ldsts = n_ldsts
+        self.bitwid = addrbitwid
 
-        self.st_i = Signal(n_int_alus, reset_less=True) # Dest R# in
-        self.ld_i = Signal(n_int_alus, reset_less=True) # oper1 R# in
+        self.st_i = Signal(n_ldsts, reset_less=True) # Dest R# in
+        self.ld_i = Signal(n_ldsts, reset_less=True) # oper1 R# in
 
-        self.g_int_ld_pend_o = Signal(n_int_alus, reset_less=True)
-        self.g_int_st_pend_o = Signal(n_int_alus, reset_less=True)
+        self.g_int_ld_pend_o = Signal(n_ldsts, reset_less=True)
+        self.g_int_st_pend_o = Signal(n_ldsts, reset_less=True)
 
-        self.st_rsel_o = Signal(n_int_alus, reset_less=True) # dest reg (bot)
-        self.ld_rsel_o = Signal(n_int_alus, reset_less=True) # src1 reg (bot)
+        self.st_rsel_o = Signal(n_ldsts, reset_less=True) # dest reg (bot)
+        self.ld_rsel_o = Signal(n_ldsts, reset_less=True) # src1 reg (bot)
 
-        self.loadable_o = Signal(n_int_alus, reset_less=True)
-        self.storable_o = Signal(n_int_alus, reset_less=True)
+        self.loadable_o = Signal(n_ldsts, reset_less=True)
+        self.storable_o = Signal(n_ldsts, reset_less=True)
 
-        self.go_ld_i = Signal(n_int_alus, reset_less=True)
-        self.go_st_i = Signal(n_int_alus, reset_less=True)
-        self.go_die_i = Signal(n_int_alus, reset_less=True)
-        self.fn_issue_i = Signal(n_int_alus, reset_less=True)
+        self.go_ld_i = Signal(n_ldsts, reset_less=True)
+        self.go_st_i = Signal(n_ldsts, reset_less=True)
+        self.go_die_i = Signal(n_ldsts, reset_less=True)
+        self.fn_issue_i = Signal(n_ldsts, reset_less=True)
+
+        # address matching
+        self.addrs_i = Array(Signal(self.bitwid, name="addrs_i%d" % i) \
+                             for i in range(n_ldsts))
+        self.addr_we_i = Signal(n_ldsts) # write-enable for incoming address
+        self.addr_en_i = Signal(n_ldsts) # address activated (0 == ignore)
 
         # Note: FURegs st_pend_o is also outputted from here, for use in WaWGrid
 
@@ -85,15 +92,22 @@ class MemFunctionUnits(Elaboratable):
         comb = m.d.comb
         sync = m.d.sync
 
-        n_intfus = self.n_int_alus
+        n_fus = self.n_ldsts
 
         # Integer FU-FU Dep Matrix
-        intfudeps = FUFUDepMatrix(n_intfus, n_intfus)
+        intfudeps = FUFUDepMatrix(n_fus, n_fus)
         m.submodules.intfudeps = intfudeps
         # Integer FU-Reg Dep Matrix
-        intregdeps = FURegDepMatrix(n_intfus, n_intfus, 1)
+        intregdeps = FUMemMatchMatrix(n_fus, self.bitwid)
         m.submodules.intregdeps = intregdeps
 
+        # ok, because we do not know in advance what the AGEN (address gen)
+        # is, we have to make a transitive dependency set.  i.e. the LD
+        # (or ST) being requested now must depend on ALL prior LDs *AND* STs.
+        # these get dropped very rapidly once AGEN is carried out.
+        # XXX TODO
+
+        # connect fureg matrix as a mem system
         comb += self.g_int_ld_pend_o.eq(intregdeps.v_rd_rsel_o)
         comb += self.g_int_st_pend_o.eq(intregdeps.v_wr_rsel_o)
 
@@ -123,6 +137,12 @@ class MemFunctionUnits(Elaboratable):
         comb += self.st_rsel_o.eq(intregdeps.dest_rsel_o)
         comb += self.ld_rsel_o.eq(intregdeps.src_rsel_o[0])
 
+        # connect address matching: these get connected to the Addr CUs
+        for i in range(self.n_ldsts):
+            comb += intregdeps.addrs_i[i].eq(self.addrs_i[i])
+        comb += intregdeps.addr_we_i.eq(self.addr_we_i)
+        comb += intregdeps.addr_en_i.eq(self.addr_en_i)
+
         return m
 
     def __iter__(self):
@@ -138,6 +158,9 @@ class MemFunctionUnits(Elaboratable):
         yield self.go_ld_i
         yield self.go_die_i
         yield self.fn_issue_i
+        yield from self.addrs_i
+        yield self.addr_we_i
+        yield self.addr_en_i
 
     def ports(self):
         return list(self)
@@ -644,6 +667,13 @@ def mem_sim(dut):
     yield dut.fn_issue_i.eq(0x0)
     yield
 
+    yield dut.addrs_i[0].eq(0x012)
+    yield dut.addrs_i[1].eq(0x012)
+    yield dut.addrs_i[2].eq(0x010)
+    yield dut.addr_en_i.eq(0x3)
+    yield
+    yield dut.addr_we_i.eq(0x3)
+    yield
     yield dut.go_ld_i.eq(0x1)
     yield
     yield dut.go_ld_i.eq(0x0)
@@ -655,7 +685,7 @@ def mem_sim(dut):
 
 
 def test_mem_fus():
-    dut = MemFunctionUnits(3)
+    dut = MemFunctionUnits(3, 11)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_mem_fus.il", "w") as f:
         f.write(vl)