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set clock freq Constant length to 32-bit in Tercel.
[soc.git]
/
src
/
soc
/
bus
/
tercel.py
diff --git
a/src/soc/bus/tercel.py
b/src/soc/bus/tercel.py
index 1e204b5a582516dabfd7a41b8544b2cc8bbef029..934fda20e584e83b18f765766bc9907a253d7f59 100644
(file)
--- a/
src/soc/bus/tercel.py
+++ b/
src/soc/bus/tercel.py
@@
-45,7
+45,7
@@
class Tercel(Elaboratable):
# TODO, sort this out.
assert clk_freq is not None
clk_freq = round(clk_freq)
- self.clk_freq = Const(clk_freq, clk_freq.bit_length())
+ self.clk_freq = Const(clk_freq,
32) #
clk_freq.bit_length())
# set up the wishbone busses
if features is None: