Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / decoder / helpers.py

diff --git a/src/soc/decoder/helpers.py b/src/soc/decoder/helpers.py
index a50d009263a839271a136ceacc3995ff44d85b63..b54bcfd86233f50a5467347458547c8e6fd7cec7 100644 (file)
--- a/src/soc/decoder/helpers.py
+++ b/src/soc/decoder/helpers.py
@@ -1,10 +1,10 @@
 import unittest
-from soc.decoder.selectable_int import SelectableInt, onebit
+from openpower.decoder.selectable_int import SelectableInt, onebit
 from nmutil.divmod import trunc_divs, trunc_rems
 from operator import floordiv, mod
-from soc.decoder.selectable_int import selectltu as ltu
-from soc.decoder.selectable_int import selectgtu as gtu
-from soc.decoder.selectable_int import check_extsign
+from openpower.decoder.selectable_int import selectltu as ltu
+from openpower.decoder.selectable_int import selectgtu as gtu
+from openpower.decoder.selectable_int import check_extsign
 
 trunc_div = floordiv
 trunc_rem = mod
@@ -36,6 +36,13 @@ def EXTS64(value):
     return SelectableInt(exts(value.value, value.bits) & ((1 << 64)-1), 64)
 
 
+def EXTS128(value):
+    """ extends sign bit out from current MSB to 128 bits
+    """
+    assert isinstance(value, SelectableInt)
+    return SelectableInt(exts(value.value, value.bits) & ((1 << 128)-1), 128)
+
+
 # signed version of MUL
 def MULS(a, b):
     if isinstance(b, int):
@@ -122,6 +129,16 @@ def le(a, b):
 def length(a):
     return len(a)
 
+
+def undefined(v):
+    """ function that, for Power spec purposes, returns undefined bits of
+        the same shape as the input bits.  however, for purposes of matching
+        POWER9's behavior returns the input bits unchanged.  this effectively
+        "marks" (tags) locations in the v3.0B spec that need to be submitted
+        for clarification.
+    """
+    return v
+
 # For these tests I tried to find power instructions that would let me
 # isolate each of these helper operations. So for instance, when I was
 # testing the MASK() function, I chose rlwinm and rldicl because if I