Auto insert instruction fields into the namespace

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 835c9b48e011ee160cc1ae252e8d375fccdb7bb7..39d99d5e4fbe4d6fec12999e48e0514e6835bdfe 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -123,16 +123,26 @@ class ISACaller:
     def memassign(self, ea, sz, val):
         self.mem.memassign(ea, sz, val)
 
-    def prep_namespace(self):
-        for name in ['SI', 'UI', 'D', 'BD']:
-            signal = getattr(self.decoder, name)
-            val = yield signal
-            self.namespace[name] = SelectableInt(val, bits=signal.width)
+    def prep_namespace(self, formname, op_fields):
+        # TODO: get field names from form in decoder*1* (not decoder2)
+        # decoder2 is hand-created, and decoder1.sigform is auto-generated
+        # from spec
+        # then "yield" fields only from op_fields rather than hard-coded
+        # list, here.
+        fields = self.decoder.sigforms[formname]
+        for name in fields._fields:
+            if name not in ["RA", "RB", "RT"]:
+                sig = getattr(fields, name)
+                val = yield sig
+                self.namespace[name] = SelectableInt(val, sig.width)
 
     def call(self, name):
-        yield from self.prep_namespace()
+        # TODO, asmregs is from the spec, e.g. add RT,RA,RB
+        # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
+        fn, read_regs, uninit_regs, write_regs, op_fields, form, asmregs \
+            = self.instrs[name]
+        yield from self.prep_namespace(form, op_fields)
 
-        function, read_regs, uninit_regs, write_regs = self.instrs[name]
         input_names = create_args(read_regs | uninit_regs)
         print(input_names)
 
@@ -144,7 +154,7 @@ class ISACaller:
             print('reading reg %d' % regnum)
             inputs.append(self.gpr(regnum))
         print(inputs)
-        results = function(self, *inputs)
+        results = fn(self, *inputs)
         print(results)
 
         if write_regs:
@@ -152,8 +162,8 @@ class ISACaller:
             for name, output in zip(output_names, results):
                 regnum = yield getattr(self.decoder, name)
                 print('writing reg %d' % regnum)
-                if isinstance(output, int):
-                    output = SelectableInt(output, 64)
+                if output.bits > 64:
+                    output = SelectableInt(output.value, 64)
                 self.gpr[regnum] = output