def memassign(self, ea, sz, val):
self.mem.memassign(ea, sz, val)
- def prep_namespace(self):
- si = yield self.decoder.SI
- self.namespace['SI'] = SelectableInt(si, bits=16)
+ def prep_namespace(self, formname, op_fields):
+ # TODO: get field names from form in decoder*1* (not decoder2)
+ # decoder2 is hand-created, and decoder1.sigform is auto-generated
+ # from spec
+ # then "yield" fields only from op_fields rather than hard-coded
+ # list, here.
+ fields = self.decoder.sigforms[formname]
+ for name in fields._fields:
+ if name not in ["RA", "RB", "RT"]:
+ sig = getattr(fields, name)
+ val = yield sig
+ self.namespace[name] = SelectableInt(val, sig.width)
def call(self, name):
- yield from self.prep_namespace()
+ # TODO, asmregs is from the spec, e.g. add RT,RA,RB
+ # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
+ fn, read_regs, uninit_regs, write_regs, op_fields, form, asmregs \
+ = self.instrs[name]
+ yield from self.prep_namespace(form, op_fields)
- function, read_regs, uninit_regs, write_regs = self.instrs[name]
input_names = create_args(read_regs | uninit_regs)
print(input_names)
inputs = []
for name in input_names:
regnum = yield getattr(self.decoder, name)
+ regname = "_" + name
+ self.namespace[regname] = regnum
print('reading reg %d' % regnum)
inputs.append(self.gpr(regnum))
print(inputs)
- results = function(self, *inputs)
+ results = fn(self, *inputs)
print(results)
- output_names = create_args(write_regs)
- for name, output in zip(output_names, results):
- regnum = yield getattr(self.decoder, name)
- print('writing reg %d' % regnum)
- self.gpr[regnum] = output.narrow(64)
+ if write_regs:
+ output_names = create_args(write_regs)
+ for name, output in zip(output_names, results):
+ regnum = yield getattr(self.decoder, name)
+ print('writing reg %d' % regnum)
+ if output.bits > 64:
+ output = SelectableInt(output.value, 64)
+ self.gpr[regnum] = output
def inject():