reduce dcache/icache number of ways, to fit into ECP5 45k resource

[soc.git] / src / soc / experiment / dcache.py

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index f2e4360abc5c68d87a6e3c923a5a5388fa0e0899..39578ebc98dd5e6f9bbe1548a62d4634cdb2ed63 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -747,10 +747,10 @@ class DCache(Elaboratable, DCacheConfig):
 
         if self.microwatt_compat:
             # reduce way sizes and num lines
-            super().__init__(NUM_LINES = 4,
+            super().__init__(NUM_LINES = 2,
                               NUM_WAYS = 1,
                               TLB_NUM_WAYS = 1,
-                              TLB_SET_SIZE=4) # XXX needs device-tree entry
+                              TLB_SET_SIZE=2) # XXX needs device-tree entry
         else:
             super().__init__()