couple of adjustments to reduce gate count in i/d-cache

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 9e63f9ac9d935ceba4f05312e18afc5aa4f90a3a..4329fd5b7fb765f58f71877eee502f88634d6a6c 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -524,9 +524,11 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
 
         # Test if pending request is a hit on any way
         hitcond = Signal()
-        comb += hitcond.eq((r.state == State.WAIT_ACK)
-                 & (req_index == r.store_index)
-                 & r.rows_valid[req_row % self.ROW_PER_LINE]
+        rowvalid = Signal()
+        comb += rowvalid.eq(r.rows_valid[req_row % self.ROW_PER_LINE])
+        comb += hitcond.eq((r.state == State.WAIT_ACK) &
+                            (req_index == r.store_index) &
+                             rowvalid
                 )
         # i_in.req asserts Decoder active
         cvb = Signal(self.NUM_WAYS)