reduce icache/dcache TLB sizes

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index ff45332d8fd9a5460464468fcefbffd9e808306f..4e40ce403e94f1536b38e269867496619676293c 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -344,8 +344,8 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
 
         XLEN = pspec.XLEN
         LINE_SIZE = 64
-        TLB_SIZE = 16
-        NUM_LINES = 16
+        TLB_SIZE = 8
+        NUM_LINES = 8
         NUM_WAYS = 2
         if self.small_cache:
             # reduce way sizes and num lines to ridiculously small