reduce TLB set size from 64 to 16 to get FPGA resource utilisation down

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 25a5adb4bbe93909f786decab78dcf3da4ea71a6..9e63f9ac9d935ceba4f05312e18afc5aa4f90a3a 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -339,6 +339,7 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
             # reduce way sizes and num lines
             ICacheConfig.__init__(self, NUM_LINES = 4,
                                         NUM_WAYS = 1,
+                                        TLB_SIZE=16 # needs device-tree update
                                  )
         else:
             ICacheConfig.__init__(self)