reduce dcache/icache number of ways, to fit into ECP5 45k resource

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index e9c8ed1b1db45b50e6eb7d6158706aaeee6ed14e..b0b674c845601d369d379e880f199ef563df4263 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -345,9 +345,9 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
             # reduce way sizes and num lines
             ICacheConfig.__init__(self, LINE_SIZE=XLEN,
                                         XLEN=XLEN,
-                                        NUM_LINES = 4,
+                                        NUM_LINES = 2,
                                         NUM_WAYS = 1,
-                                        TLB_SIZE=4 # needs device-tree update
+                                        TLB_SIZE=2 # needs device-tree update
                                  )
         else:
             ICacheConfig.__init__(self, LINE_SIZE=XLEN, XLEN=XLEN)