rename PLRU modules to avoid conflict in microwatt

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 5523c50ca0fd3b1e0b7a7dcf5d30978db4fd77fe..e9c8ed1b1db45b50e6eb7d6158706aaeee6ed14e 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -419,7 +419,8 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
             return
 
 
-        m.submodules.plrus = plru = PLRUs(self.NUM_LINES, self.WAY_BITS)
+        m.submodules.plrus = plru = PLRUs("itag", self.NUM_LINES,
+                                                  self.WAY_BITS)
         comb += plru.way.eq(r.hit_way)
         comb += plru.valid.eq(r.hit_valid)
         comb += plru.index.eq(self.get_index(r.hit_nia))