convert from public static functions/properties for regspecs

[soc.git] / src / soc / fu / alu / pipe_data.py

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index 1e552ff6f0ed937f06e17295b52574dc776cb409..572ec9a6bcd18c22202f4a100531e6f843975889 100644 (file)
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -3,30 +3,36 @@ from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
 
 
 class ALUInputData(FUBaseData):
-    regspec = [('INT', 'ra', '0:63'),  # RA
-               ('INT', 'rb', '0:63'),  # RB/immediate
-               ('XER', 'xer_so', '32'),  # XER bit 32: SO
-               ('XER', 'xer_ca', '34,45')]  # XER bit 34/45: CA/CA32
-
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
         self.a, self.b = self.ra, self.rb
 
+    @property
+    def regspec(self):
+        return [('INT', 'ra', self.intrange),  # RA
+               ('INT', 'rb', self.intrange),  # RB/immediate
+               ('XER', 'xer_so', '32'),  # XER bit 32: SO
+               ('XER', 'xer_ca', '34,45')]  # XER bit 34/45: CA/CA32
+
+
 
 class ALUOutputData(FUBaseData):
-    regspec = [('INT', 'o', '0:63'),
+    def __init__(self, pspec):
+        super().__init__(pspec, True)
+        # convenience
+        self.cr0 = self.cr_a
+
+    @property
+    def regspec(self):
+        return [('INT', 'o', self.intrange),
                ('CR', 'cr_a', '0:3'),
                ('XER', 'xer_ca', '34,45'),  # bit0: ca, bit1: ca32
                ('XER', 'xer_ov', '33,44'),  # bit0: ov, bit1: ov32
                ('XER', 'xer_so', '32')]
 
-    def __init__(self, pspec):
-        super().__init__(pspec, True)
-        # convenience
-        self.cr0 = self.cr_a
 
 
 class ALUPipeSpec(CommonPipeSpec):
-    regspec = (ALUInputData.regspec, ALUOutputData.regspec)
     opsubsetkls = CompALUOpSubset
+    regspecklses = (ALUInputData, ALUOutputData)