remove grev, leaving tests for later use with grevlut

[soc.git] / src / soc / fu / shift_rot / formal / proof_main_stage.py

diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py
index 7ef3258fabb04fa254b65df395b1c5945e4c3d46..379211d623a01259f77c90229cae0d57f40228a7 100644 (file)
--- a/src/soc/fu/shift_rot/formal/proof_main_stage.py
+++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py
@@ -39,8 +39,9 @@ class TstOp(enum.Enum):
     RLCR = MicrOp.OP_RLCR
     EXTSWSLI = MicrOp.OP_EXTSWSLI
     TERNLOG = MicrOp.OP_TERNLOG
-    GREV32 = MicrOp.OP_GREV, 32
-    GREV64 = MicrOp.OP_GREV, 64
+    # grev removed -- leaving code for later use in grevlut
+    # GREV32 = MicrOp.OP_GREV, 32
+    # GREV64 = MicrOp.OP_GREV, 64
 
     @property
     def op(self):
@@ -316,6 +317,7 @@ class Driver(Elaboratable):
                     m.d.comb += Assert(dut.o.o.data[i] == lut[j])
         m.d.comb += Assert(dut.o.xer_ca.data == 0)
 
+    # grev removed -- leaving code for later use in grevlut
     def _check_grev32(self, m, dut):
         m.d.comb += Assume(dut.i.ctx.op.is_32bit)
         # assert zero-extended
@@ -326,6 +328,7 @@ class Driver(Elaboratable):
         m.d.comb += Assert((dut.o.o.data >> i)[0] == (dut.i.ra >> idx)[0])
         m.d.comb += Assert(dut.o.xer_ca.data == 0)
 
+    # grev removed -- leaving code for later use in grevlut
     def _check_grev64(self, m, dut):
         m.d.comb += Assume(~dut.i.ctx.op.is_32bit)
         i = Signal(6)
@@ -368,9 +371,11 @@ class ALUTestCase(FHDLTestCase):
     def test_ternlog(self):
         self.run_it(TstOp.TERNLOG)
 
+    @unittest.skip("grev removed -- leaving code for later use in grevlut")
     def test_grev32(self):
         self.run_it(TstOp.GREV32)
 
+    @unittest.skip("grev removed -- leaving code for later use in grevlut")
     def test_grev64(self):
         self.run_it(TstOp.GREV64)