add alternative pc_reset argument to issuer_verilog.py

[soc.git] / src / soc / simple / core.py

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 0479508adf1e6aa915173a114966f97a1cd2702b..20a396c39000e52baca7ba47024df045db04262a 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -161,9 +161,12 @@ class NonProductionCore(ControlBase):
 
         # alternative reset values for STATE regs
         self.msr_at_reset = 0x0
+        self.pc_at_reset = 0x0
         if hasattr(pspec, "msr_reset") and isinstance(pspec.msr_reset, int):
             self.msr_at_reset = pspec.msr_reset
-        state_resets = [0x0,               # PC at reset
+        if hasattr(pspec, "pc_reset") and isinstance(pspec.pc_reset, int):
+            self.pc_at_reset = pspec.pc_reset
+        state_resets = [self.pc_at_reset,  # PC at reset
                         self.msr_at_reset, # MSR at reset
                         0x0,               # SVSTATE at reset
                         0x0,               # DEC at reset