add ldst PortInterface misalign unit test (underway)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 26 May 2021 13:22:45 +0000 (14:22 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 26 May 2021 13:22:49 +0000 (14:22 +0100)
commit1429bf1d4b0f07c756f242a14271a59cca206347
tree0d88780e1bc293da33445d3c40203e498d5a10ef
parentc6ad07b572b06e2606e404738284e01c3c791dd5
add ldst PortInterface misalign unit test (underway)
src/soc/experiment/test/test_ldst_pi_misalign.py [new file with mode: 0644]
src/soc/litex/florent