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(parent: 6ffbcf1) | patch
Implement 1W/1R with a transparent (or not) read port.
authorCesar Strauss <cestrauss@gmail.com>
Sun, 10 Apr 2022 12:24:19 +0000 (09:24 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sun, 10 Apr 2022 12:24:19 +0000 (09:24 -0300)
commit29a6c5c3bb6a211a2e7031fcca7f86f39720f467
treee6980486d9c194cd160f286d3596caa7521ccc74tree
parent6ffbcf1a8dab6eb83042483cec2a5c4c018d46ddcommit | diff
Implement 1W/1R with a transparent (or not) read port.

Seems that it's just a matter of the underlying memories being
transparent (or not).
src/soc/regfile/sram_wrapper.py diff | blob | history