Add a Single R/W Port SRAM model
authorCesar Strauss <cestrauss@gmail.com>
Sun, 13 Mar 2022 11:56:24 +0000 (08:56 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sun, 13 Mar 2022 12:08:23 +0000 (09:08 -0300)
commit44150c000c3449ee379cf7287ff633e69633af0a
treeaa60e6c21115b013736dc7dc460adad2fb51bcf4
parent20fcdd7b7dbccd5512a683e2bbcf318f8e084250
Add a Single R/W Port SRAM model

Begin making unit tests by checking with Yosys.
src/soc/regfile/sram_wrapper.py [new file with mode: 0644]