soc.git
2 years agoAdd a Single R/W Port SRAM model
Cesar Strauss [Sun, 13 Mar 2022 11:56:24 +0000 (08:56 -0300)]
Add a Single R/W Port SRAM model

Begin making unit tests by checking with Yosys.

2 years agoadd extra pipeline stages to ALU FU to make timing
Luke Kenneth Casson Leighton [Sat, 12 Mar 2022 16:08:29 +0000 (16:08 +0000)]
add extra pipeline stages to ALU FU to make timing

2 years agointroduce extra register of delay to split combinatorial loops
Luke Kenneth Casson Leighton [Sat, 12 Mar 2022 15:45:16 +0000 (15:45 +0000)]
introduce extra register of delay to split combinatorial loops
by making fetch_ic_i_valid sync

2 years agoRevert "read last row from r.wb.adr not r.req_adr in icache"
Luke Kenneth Casson Leighton [Sat, 12 Mar 2022 14:43:19 +0000 (14:43 +0000)]
Revert "read last row from r.wb.adr not r.req_adr in icache"

This reverts commit 1bcb90676398c8fa0c309c3c7ed3c9ef306c577e.

2 years agoRevert "store cur_state.pc+4 in separate register to help reduce"
Luke Kenneth Casson Leighton [Sat, 12 Mar 2022 14:13:15 +0000 (14:13 +0000)]
Revert "store cur_state.pc+4 in separate register to help reduce"

This reverts commit d9b58d594ede33db2b0290d7edf8e062f5e91460.

2 years agostore cur_state.pc+4 in separate register to help reduce
Luke Kenneth Casson Leighton [Sat, 12 Mar 2022 13:22:39 +0000 (13:22 +0000)]
store cur_state.pc+4 in separate register to help reduce
combinatorial chains

2 years agoread last row from r.wb.adr not r.req_adr in icache
Luke Kenneth Casson Leighton [Sat, 12 Mar 2022 13:22:15 +0000 (13:22 +0000)]
read last row from r.wb.adr not r.req_adr in icache

2 years agoremove stbs_done in icache.py
Luke Kenneth Casson Leighton [Tue, 8 Mar 2022 16:47:27 +0000 (16:47 +0000)]
remove stbs_done in icache.py

2 years agoremove ld_stbs_done from dcache: not needed
Luke Kenneth Casson Leighton [Tue, 8 Mar 2022 15:46:15 +0000 (15:46 +0000)]
remove ld_stbs_done from dcache: not needed

2 years agowork-in-progress on sdram opencores wrapper
Luke Kenneth Casson Leighton [Tue, 8 Mar 2022 15:45:49 +0000 (15:45 +0000)]
work-in-progress on sdram opencores wrapper

2 years agoCopy the startup delay from issuer.py to inorder.py
Cesar Strauss [Sun, 6 Mar 2022 18:00:37 +0000 (15:00 -0300)]
Copy the startup delay from issuer.py to inorder.py

Fixes TestIssuerInternalInOrder hanging at startup.

2 years agoattempting to introduce an extra few clock cycles delay on power-up
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 17:43:39 +0000 (17:43 +0000)]
attempting to introduce an extra few clock cycles delay on power-up
this may help with initialisation of I-Cache SRAM which is combinatorial.
maybe

2 years agofor lulz make I-Cache possible to set to 32-bit (XLEN=32)
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 21:23:12 +0000 (21:23 +0000)]
for lulz make I-Cache possible to set to 32-bit (XLEN=32)

2 years agobit_length is 1 more than needed: subtract 1 from XLEN first
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 19:50:33 +0000 (19:50 +0000)]
bit_length is 1 more than needed: subtract 1 from XLEN first

2 years agofix up shift_rot test_pipe_caller to new regspeckls style
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 19:34:05 +0000 (19:34 +0000)]
fix up shift_rot test_pipe_caller to new regspeckls style

2 years agoconvert shift_rot pipeline to XLEN=32/64
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 19:25:54 +0000 (19:25 +0000)]
convert shift_rot pipeline to XLEN=32/64

2 years agofix up Logical pipeline to produce HDL with XLEN=32
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 19:16:35 +0000 (19:16 +0000)]
fix up Logical pipeline to produce HDL with XLEN=32
fix Logical test_pipe_caller.py to use new regspeckls style

2 years agowhoops ALU common output target must be XLEN-bit,
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 18:48:28 +0000 (18:48 +0000)]
whoops ALU common output target must be XLEN-bit,
cannot set to length of output (o) using Signal.like

2 years agoset up dummy parent_pspec to pass XLEN=64 in
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 18:41:43 +0000 (18:41 +0000)]
set up dummy parent_pspec to pass XLEN=64 in
ALU test_pipe_spec.py

2 years agostart on converting MUL and DIV pipelines to XLEN
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 18:37:37 +0000 (18:37 +0000)]
start on converting MUL and DIV pipelines to XLEN

2 years agoconvert from public static functions/properties for regspecs
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 18:17:08 +0000 (18:17 +0000)]
convert from public static functions/properties for regspecs
to member functions to obtain regspecs
this allows pspec (containing XLEN) to be passed to the regspecs,
which in turn allows them to be dynamically set by issuer_verilog.py
and unit tests

2 years agofix ALU with XLEN=32, carry and overflow
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 18:09:13 +0000 (18:09 +0000)]
fix ALU with XLEN=32, carry and overflow

2 years agouse XLEN in Function Units (starting with ALU)
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 18:01:54 +0000 (18:01 +0000)]
use XLEN in Function Units (starting with ALU)

2 years agoadd XLEN to issuer_verilog.py defaults to 64
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 17:31:51 +0000 (17:31 +0000)]
add XLEN to issuer_verilog.py defaults to 64

2 years agoadd XLEN option to regfiles via pspec
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 17:17:07 +0000 (17:17 +0000)]
add XLEN option to regfiles via pspec

2 years agoadd running instructions
Jacob Lifshay [Thu, 24 Feb 2022 03:33:13 +0000 (19:33 -0800)]
add running instructions

2 years agoadd formal proof for shift/rot o.ok
Jacob Lifshay [Thu, 24 Feb 2022 03:28:02 +0000 (19:28 -0800)]
add formal proof for shift/rot o.ok

2 years agoclean up code
Jacob Lifshay [Thu, 24 Feb 2022 03:16:17 +0000 (19:16 -0800)]
clean up code

2 years agoadd formal proof for OP_RLCR
Jacob Lifshay [Thu, 24 Feb 2022 03:12:49 +0000 (19:12 -0800)]
add formal proof for OP_RLCR

2 years agoadd formal proof for OP_RLCL
Jacob Lifshay [Thu, 24 Feb 2022 03:01:49 +0000 (19:01 -0800)]
add formal proof for OP_RLCL

2 years agoadd formal proof for OP_RLC
Jacob Lifshay [Thu, 24 Feb 2022 02:40:48 +0000 (18:40 -0800)]
add formal proof for OP_RLC

2 years agoforgot to pass cix (cache-inhibited) through to LD/ST which was
Luke Kenneth Casson Leighton [Wed, 23 Feb 2022 17:17:50 +0000 (17:17 +0000)]
forgot to pass cix (cache-inhibited) through to LD/ST which was
causing D-Cache to make too many read/writes and overrun wishbone
bus addressing on peripherals.
D-Cache always (for non-cache-inhibited) makes 8 64-bit requests:
if a memory-mapped peripheral has only say 3 32-bit CSRs then the
additional requests beyond the range of the peripheral will cause
a permanent lock-up

2 years agospeed up shift/rot formal proof by running stuff in parallel
Jacob Lifshay [Tue, 22 Feb 2022 09:33:16 +0000 (01:33 -0800)]
speed up shift/rot formal proof by running stuff in parallel

it now runs in about 1m30s in `pytest -n auto <file>.py`

also start work on rewriting proofs to hopefully work better, all
of grev, ternlog, extswsli, shl, and shr are completed.

2 years agoagain reduce combinatorial chains, similar to Trap pipeline,
Luke Kenneth Casson Leighton [Mon, 21 Feb 2022 00:26:14 +0000 (00:26 +0000)]
again reduce combinatorial chains, similar to Trap pipeline,
introduce dummy passthrough stage in Branch pipeline

2 years agoadd syn_ramstyle "block_ram" attributes and reduce i/d-cache sizes again
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 23:58:58 +0000 (23:58 +0000)]
add syn_ramstyle "block_ram" attributes and reduce i/d-cache sizes again

2 years agosame as shiftrot, split out separate pipelines for logical
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 23:51:32 +0000 (23:51 +0000)]
same as shiftrot, split out separate pipelines for logical
stages in order to meet FPGA timing

2 years agoput LDST go-store on a 1-clock delay to help with combinatorial chains
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 23:38:13 +0000 (23:38 +0000)]
put LDST go-store on a 1-clock delay to help with combinatorial chains

2 years agoname core_stop and terminated_o synchronous to potentially help
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 23:28:50 +0000 (23:28 +0000)]
name core_stop and terminated_o synchronous to potentially help
cut down on combinatorial chains

2 years agonope, it's perfectly fine
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 22:20:21 +0000 (22:20 +0000)]
nope, it's perfectly fine

Revert "weird exception, oe not found in the shiftrot input record"

This reverts commit 264cc7fd7d7547e1e19424b8f8fd0fbfea29cec5.

2 years agoweird exception, oe not found in the shiftrot input record
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 22:17:18 +0000 (22:17 +0000)]
weird exception, oe not found in the shiftrot input record

Revert "separate out shiftrot stages due to size of main stage being so large"

This reverts commit 87d6b84e96fb62cda16cc9f335e34fe15ad6cd97.

2 years agoseparate out shiftrot stages due to size of main stage being so large
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 22:09:42 +0000 (22:09 +0000)]
separate out shiftrot stages due to size of main stage being so large

2 years agoadd blockram style to regfile Memory
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 20:50:22 +0000 (20:50 +0000)]
add blockram style to regfile Memory

2 years agouse block_ram attribute for FPGA synthesis
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 20:49:36 +0000 (20:49 +0000)]
use block_ram attribute for FPGA synthesis

2 years agoreduce number of d-cache lines in microwatt fpga mode
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 19:42:44 +0000 (19:42 +0000)]
reduce number of d-cache lines in microwatt fpga mode

2 years agocouple of adjustments to reduce gate count in i/d-cache
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 19:41:42 +0000 (19:41 +0000)]
couple of adjustments to reduce gate count in i/d-cache

2 years agoadd SDRAM Configuration Record
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 19:41:23 +0000 (19:41 +0000)]
add SDRAM Configuration Record

2 years agoreduce TLB set size from 64 to 16 to get FPGA resource utilisation down
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 11:53:06 +0000 (11:53 +0000)]
reduce TLB set size from 64 to 16 to get FPGA resource utilisation down

2 years agodrastically reduce I-Cache size in microwatt-compat mode
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 11:41:29 +0000 (11:41 +0000)]
drastically reduce I-Cache size in microwatt-compat mode
should really be called "small FPGA mode" or something

2 years agoparameterise I-Cache similar to D-Cache. lots of "self."
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 11:36:19 +0000 (11:36 +0000)]
parameterise I-Cache similar to D-Cache. lots of "self."
all over the place. yuk.

2 years agoadd grev
Jacob Lifshay [Fri, 18 Feb 2022 06:01:41 +0000 (22:01 -0800)]
add grev

2 years agoadd opencores SDRAM verilog wrapper
Luke Kenneth Casson Leighton [Thu, 17 Feb 2022 17:09:21 +0000 (17:09 +0000)]
add opencores SDRAM verilog wrapper

2 years agooof. big update to DCache to accept config parameters
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 16:18:05 +0000 (16:18 +0000)]
oof. big update to DCache to accept config parameters

2 years agoconnect UART16550 pins if given
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 16:17:22 +0000 (16:17 +0000)]
connect UART16550 pins if given

2 years agofor *write* the counter-address on downconvert was correct
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 20:07:35 +0000 (20:07 +0000)]
for *write* the counter-address on downconvert was correct
but for *read* it has to be pre-advanced (if that makes any sense)

2 years agoadd wishbone downconvert "skip" of slave sel so that action
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 19:35:14 +0000 (19:35 +0000)]
add wishbone downconvert "skip" of slave sel so that action
is not taken

2 years agoadd SysCon reg_info, has uart and has large SYSCON
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 19:24:37 +0000 (19:24 +0000)]
add SysCon reg_info, has uart and has large SYSCON

2 years agosigh, stall was not working but actually turns out that
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 19:20:36 +0000 (19:20 +0000)]
sigh, stall was not working but actually turns out that
the downconvert counter was not being set properly (one cycle late)

2 years agoadd option to specify UART16550 width (32/8)
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 15:28:48 +0000 (15:28 +0000)]
add option to specify UART16550 width (32/8)

2 years agoadd beginnings of syscon bus peripheral
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 13:51:53 +0000 (13:51 +0000)]
add beginnings of syscon bus peripheral

2 years agoupdate comments
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 11:42:26 +0000 (11:42 +0000)]
update comments

2 years agoresolve WBDownConvert ack issues when stall is active
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 01:35:06 +0000 (01:35 +0000)]
resolve WBDownConvert ack issues when stall is active

2 years agostrip first 3 bits of WB address from microwatt d/i-bus, bug in microwatt
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 14:22:48 +0000 (14:22 +0000)]
strip first 3 bits of WB address from microwatt d/i-bus, bug in microwatt

2 years agoslave sends stall signal, master receives, in
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 14:22:14 +0000 (14:22 +0000)]
slave sends stall signal, master receives, in
WBDownConvert

2 years agosort out ExternalCore signal names
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 14:02:59 +0000 (14:02 +0000)]
sort out ExternalCore signal names

2 years agoadd wishbone slave signal to downconvert if present
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 14:02:40 +0000 (14:02 +0000)]
add wishbone slave signal to downconvert if present

2 years agoadd external core verilog wrapper, ironically around Libre-SOC
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 13:08:56 +0000 (13:08 +0000)]
add external core verilog wrapper, ironically around Libre-SOC
(as well as Microwatt)

2 years agobugfixing for ls2 imports of uart16550
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:24:58 +0000 (14:24 +0000)]
bugfixing for ls2 imports of uart16550

2 years agoRevert "remove dummy trap pipeline"
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 18:06:20 +0000 (18:06 +0000)]
Revert "remove dummy trap pipeline"

This reverts commit de3765400532be229ed4dd8a1d9fdcf1b4bca0ef.

2 years agoRevert "doh"
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 18:06:10 +0000 (18:06 +0000)]
Revert "doh"

This reverts commit 26fdc967b91945d102c4efceaba18cfb1506b08a.

2 years agoAdded optional reverse arg to send TDI data MSB-first
Andrey Miroshnikov [Thu, 10 Feb 2022 15:50:20 +0000 (15:50 +0000)]
Added optional reverse arg to send TDI data MSB-first

2 years agoadd opencores uart16550 instance wrapper
Luke Kenneth Casson Leighton [Wed, 9 Feb 2022 12:22:37 +0000 (12:22 +0000)]
add opencores uart16550 instance wrapper

2 years agocorrect path for make target microwatt_external_core
Tobias Platen [Tue, 1 Feb 2022 18:13:33 +0000 (18:13 +0000)]
correct path for make target microwatt_external_core

2 years agofix bug in itlb_valid SRLatch set/reset, a bit weird but it works
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 20:38:45 +0000 (20:38 +0000)]
fix bug in itlb_valid SRLatch set/reset, a bit weird but it works

2 years agowhoops tlb_valids in ICache is a combinatorial-get/set
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 16:09:12 +0000 (16:09 +0000)]
whoops tlb_valids in ICache is a combinatorial-get/set
set SRLatch sync=False

2 years agoconvert TLBValidArray in ICache to SRLatch
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:57:56 +0000 (15:57 +0000)]
convert TLBValidArray in ICache to SRLatch

2 years agoadd microwatt external core build target to Makefile
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:47:06 +0000 (15:47 +0000)]
add microwatt external core build target to Makefile

2 years agouse an SRLatch for cache_valids, at least it reduces graphviz size
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:29:44 +0000 (15:29 +0000)]
use an SRLatch for cache_valids, at least it reduces graphviz size

2 years agouse Memory for cache tags in dcache
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:06:56 +0000 (15:06 +0000)]
use Memory for cache tags in dcache

2 years agouse Memory for cache_tags in icache
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:06:36 +0000 (15:06 +0000)]
use Memory for cache_tags in icache

2 years agodoh
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:05:37 +0000 (15:05 +0000)]
doh

2 years agoremove dummy trap pipeline
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:02:37 +0000 (15:02 +0000)]
remove dummy trap pipeline

2 years agoremove combinatorial loop from MultiCompUnit
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 14:59:45 +0000 (14:59 +0000)]
remove combinatorial loop from MultiCompUnit
actually not a loop due to an SRLatch but synth tools still think it is

2 years agobreak out cache_tags and cache_valids (again) this time in dcache
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 22:18:26 +0000 (22:18 +0000)]
break out cache_tags and cache_valids (again) this time in dcache

2 years agoremove CacheTagArray in icache.py
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 22:08:38 +0000 (22:08 +0000)]
remove CacheTagArray in icache.py

2 years agocreate Memory for Cache Tags in I-Cache
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 22:03:24 +0000 (22:03 +0000)]
create Memory for Cache Tags in I-Cache
another huge reduction in number of LUT4s, uses (again) a
combinatorial-read sync-write

2 years agoremove unneeded parameter
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 21:30:34 +0000 (21:30 +0000)]
remove unneeded parameter

2 years agoadd Array of CacheValids back in, so as to reduce LUT4 usage
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 21:28:52 +0000 (21:28 +0000)]
add Array of CacheValids back in, so as to reduce LUT4 usage

2 years agotagset is a local Signal in ICache
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 21:11:09 +0000 (21:11 +0000)]
tagset is a local Signal in ICache

2 years agoidentify combinatorial loop signals in MultiCompUnit, TODO resolve
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 21:10:55 +0000 (21:10 +0000)]
identify combinatorial loop signals in MultiCompUnit, TODO resolve

2 years agouse nmigen Memory in I-Cache for TLB Lookups
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 18:16:37 +0000 (18:16 +0000)]
use nmigen Memory in I-Cache for TLB Lookups
surprisingly this makes the Libre-SOC core *50% faster* than microwatt
when running under verilator, despite only being a FSM

2 years agoput itlb_valid back, ready for conversion to Memory, in ICache
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 17:49:17 +0000 (17:49 +0000)]
put itlb_valid back, ready for conversion to Memory, in ICache

2 years agoconvert CacheRAM to Memory, acts much faster now
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 16:51:41 +0000 (16:51 +0000)]
convert CacheRAM to Memory, acts much faster now

2 years agoexplanatory comment when page hit is the same for stores
Luke Kenneth Casson Leighton [Sat, 29 Jan 2022 16:43:56 +0000 (16:43 +0000)]
explanatory comment when page hit is the same for stores

2 years agouse right offset in dcache wb address
Luke Kenneth Casson Leighton [Sat, 29 Jan 2022 14:32:23 +0000 (14:32 +0000)]
use right offset in dcache wb address
happened to be the same value but best to be safe, eh?

2 years agore-examining dcache.vhdl, still did not get the store-page
Luke Kenneth Casson Leighton [Sat, 29 Jan 2022 13:48:19 +0000 (13:48 +0000)]
re-examining dcache.vhdl, still did not get the store-page
address quite right

2 years agobug in dcache.py where when two stores occur in the same real page
Luke Kenneth Casson Leighton [Sat, 29 Jan 2022 10:17:42 +0000 (10:17 +0000)]
bug in dcache.py where when two stores occur in the same real page
the address is corrupted.

2 years agoin LoadStore1 capture the address for misaligned dual ld/sts in
Luke Kenneth Casson Leighton [Fri, 28 Jan 2022 19:33:13 +0000 (19:33 +0000)]
in LoadStore1 capture the address for misaligned dual ld/sts in
a different way.
something very strange going on with misaligned stores: the address
is advancing far too far under certain circumstances (by 128) which
could just be an MMU / PTE lookup to a different table.

2 years agosort out misaligned store in LoadStore1
Luke Kenneth Casson Leighton [Fri, 28 Jan 2022 03:19:40 +0000 (03:19 +0000)]
sort out misaligned store in LoadStore1

2 years agofor second aligned request truncate address to nearest dword
Luke Kenneth Casson Leighton [Thu, 27 Jan 2022 10:49:14 +0000 (10:49 +0000)]
for second aligned request truncate address to nearest dword
this ensures that DAR gets set correctly if a pagefault 0x300 occurs

2 years agoadd license and copyright header to dcache.py,
Luke Kenneth Casson Leighton [Tue, 25 Jan 2022 00:43:56 +0000 (00:43 +0000)]
add license and copyright header to dcache.py,
extracted authors from git history for the file, but made sure to
credit the original dcache.vhdl as being from microwatt and its
license being CC4