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(parent: 38a29f1) | patch
attempting to introduce an extra few clock cycles delay on power-up
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 28 Feb 2022 17:43:39 +0000 (17:43 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 28 Feb 2022 17:43:39 +0000 (17:43 +0000)
commitcc9d98a1dcc6c307c4a716fab0bbddb11ac9be39
tree05984e62df465673ae4df649936ebbf508cf0170tree
parent38a29f18d527c5d52ba7459d0e9e5d9127e80667commit | diff
attempting to introduce an extra few clock cycles delay on power-up
this may help with initialisation of I-Cache SRAM which is combinatorial.
maybe
src/soc/simple/issuer.py diff | blob | history