use block_ram attribute for FPGA synthesis
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 18 Feb 2022 20:49:36 +0000 (20:49 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 18 Feb 2022 20:49:36 +0000 (20:49 +0000)
commit348b371b5084f0eda168b31aefb9088a2c24a1ae
tree757de674d26f6596efb6d3bd36e66026e3d1b4e4
parentfdd55337edc5856dc5ae0c35cd6ad28151bfc441
use block_ram attribute for FPGA synthesis
src/soc/experiment/cache_ram.py
src/soc/experiment/dcache.py
src/soc/experiment/icache.py