git.libre-soc.org Git - soc.git/history - src/soc/experiment/cache

2022-02-18	Luke Kenneth Casso...	use block_ram attribute for FPGA synthesis	blob \| commitdiff \| raw
2022-01-30	Luke Kenneth Casso...	convert CacheRAM to Memory, acts much faster now	blob \| commitdiff \| raw \| diff to current
2021-05-13	Luke Kenneth Casso...	yet more debug log stuff for DCache, this time on Cache...	blob \| commitdiff \| raw \| diff to current
2021-05-12	Luke Kenneth Casso...	no need for sel0	blob \| commitdiff \| raw \| diff to current
2021-04-22	Luke Kenneth Casso...	add debugging and buffering to CacheRam	blob \| commitdiff \| raw \| diff to current
2020-09-11	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-09-10	Luke Kenneth Casso...	eek, big sort-out of syntax errors in dcache.py, now...	blob \| commitdiff \| raw \| diff to current
2020-09-10	Luke Kenneth Casso...	starting on dcache syntax errors	blob \| commitdiff \| raw \| diff to current
2020-09-10	Luke Kenneth Casso...	add PLRU microwatt conversion	blob \| commitdiff \| raw \| diff to current
2020-09-07	Luke Kenneth Casso...	add start on cache_ram.vhdl to nmigen conversion	blob \| commitdiff \| raw \| diff to current