use block_ram attribute for FPGA synthesis

[soc.git] / src / soc / experiment / cache_ram.py

diff --git a/src/soc/experiment/cache_ram.py b/src/soc/experiment/cache_ram.py
index a79b68723a566e8bfcc88c97033949c8453ad3ec..784b9a8151fac8578dca8a1b95404480d9e509f3 100644 (file)
--- a/src/soc/experiment/cache_ram.py
+++ b/src/soc/experiment/cache_ram.py
@@ -32,7 +32,8 @@ class CacheRam(Elaboratable):
         # set up the Cache RAM Memory and create one read and one write port
         # the read port is *not* transparent (does not pass write-thru-read)
         #attribute ram_style of ram : signal is "block";
-        ram = Memory(depth=SIZE, width=WIDTH)
+        ram = Memory(depth=SIZE, width=WIDTH,
+                     attrs={'syn_ramstyle': "block_ram"})
         m.submodules.rdport = rdport = ram.read_port(transparent=False)
         m.submodules.wrport = wrport = ram.write_port(granularity=8)