add syn_ramstyle "block_ram" attributes and reduce i/d-cache sizes again

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index ce1967bd771461f9c2d75c733953d140a37daded..9e75cc01eb59ee42c71ffafdbcec5795c5ff12cb 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -747,10 +747,10 @@ class DCache(Elaboratable, DCacheConfig):
 
         if self.microwatt_compat:
             # reduce way sizes and num lines
-            super().__init__(NUM_LINES = 8,
+            super().__init__(NUM_LINES = 4,
                               NUM_WAYS = 1,
                               TLB_NUM_WAYS = 1,
-                              TLB_SET_SIZE=16) # XXX needs device-tree entry
+                              TLB_SET_SIZE=4) # XXX needs device-tree entry
         else:
             super().__init__()
 

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 8e457be57a8083d30951d109cc4d47efca95edc0..6ed9ed4458aa71a8977a9a507c3c1c34db9bde51 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -339,7 +339,7 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
             # reduce way sizes and num lines
             ICacheConfig.__init__(self, NUM_LINES = 4,
                                         NUM_WAYS = 1,
-                                        TLB_SIZE=16 # needs device-tree update
+                                        TLB_SIZE=4 # needs device-tree update
                                  )
         else:
             ICacheConfig.__init__(self)

diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py
index 07cee2dd6773eb0644da0f9b5216d4f0a1dde7f6..2427a680a94ad5f7dac71b013579dba05bfea27c 100644 (file)
--- a/src/soc/regfile/regfile.py
+++ b/src/soc/regfile/regfile.py
@@ -56,7 +56,8 @@ class Register(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        self.reg = reg = Signal(self.width, name="reg", reset=self.reset)
+        self.reg = reg = Signal(self.width, name="reg", reset=self.reset,
+                                attrs={'syn_ramstyle': "block_ram"})
 
         if self.synced:
             domain = m.d.sync
@@ -290,7 +291,9 @@ class RegFile(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         bsz = int(log(self.width) / log(2))
-        regs = Array(Signal(self.width, name="reg") for _ in range(self.depth))
+        regs = Array(Signal(self.width, name="reg",
+                            attrs={'syn_ramstyle': "block_ram"}) \
+                    for _ in range(self.depth))
 
         # read ports. has write-through detection (returns data written)
         for rp in self._rdports: