same as shiftrot, split out separate pipelines for logical

stages in order to meet FPGA timing

diff --git a/src/soc/fu/logical/pipeline.py b/src/soc/fu/logical/pipeline.py
index a16bd78acab1c6c65702368ddd28b5a2f07f1dc1..a0f00d1dcd6f473b77cb852d6200ccb78c982272 100644 (file)
--- a/src/soc/fu/logical/pipeline.py
+++ b/src/soc/fu/logical/pipeline.py
@@ -8,11 +8,15 @@ from soc.fu.logical.output_stage import LogicalOutputStage
 class LogicalStages1(PipeModBaseChain):
     def get_chain(self):
         inp = LogicalInputStage(self.pspec)
+        return [inp]
+
+class LogicalStages2(PipeModBaseChain):
+    def get_chain(self):
         main = LogicalMainStage(self.pspec)
-        return [inp, main]
+        return [main]
 
 
-class LogicalStages2(PipeModBaseChain):
+class LogicalStages3(PipeModBaseChain):
     def get_chain(self):
         out = LogicalOutputStage(self.pspec)
         return [out]
@@ -24,11 +28,13 @@ class LogicalBasePipe(ControlBase):
         self.pspec = pspec
         self.pipe1 = LogicalStages1(pspec)
         self.pipe2 = LogicalStages2(pspec)
-        self._eqs = self.connect([self.pipe1, self.pipe2])
+        self.pipe3 = LogicalStages3(pspec)
+        self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
 
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
         m.submodules.logical_pipe1 = self.pipe1
         m.submodules.logical_pipe2 = self.pipe2
+        m.submodules.logical_pipe3 = self.pipe3
         m.d.comb += self._eqs
         return m