1 from nmutil
.singlepipe
import ControlBase
2 from nmutil
.pipemodbase
import PipeModBaseChain
3 from soc
.fu
.logical
.input_stage
import LogicalInputStage
4 from soc
.fu
.logical
.main_stage
import LogicalMainStage
5 from soc
.fu
.logical
.output_stage
import LogicalOutputStage
8 class LogicalStages1(PipeModBaseChain
):
10 inp
= LogicalInputStage(self
.pspec
)
13 class LogicalStages2(PipeModBaseChain
):
15 main
= LogicalMainStage(self
.pspec
)
19 class LogicalStages3(PipeModBaseChain
):
21 out
= LogicalOutputStage(self
.pspec
)
25 class LogicalBasePipe(ControlBase
):
26 def __init__(self
, pspec
):
27 ControlBase
.__init
__(self
)
29 self
.pipe1
= LogicalStages1(pspec
)
30 self
.pipe2
= LogicalStages2(pspec
)
31 self
.pipe3
= LogicalStages3(pspec
)
32 self
._eqs
= self
.connect([self
.pipe1
, self
.pipe2
, self
.pipe3
])
34 def elaborate(self
, platform
):
35 m
= ControlBase
.elaborate(self
, platform
)
36 m
.submodules
.logical_pipe1
= self
.pipe1
37 m
.submodules
.logical_pipe2
= self
.pipe2
38 m
.submodules
.logical_pipe3
= self
.pipe3