Add separate memory clock register to SYSCON
authorRaptor Engineering Development Team <support@raptorengineering.com>
Thu, 14 Apr 2022 00:56:47 +0000 (19:56 -0500)
committerRaptor Engineering Development Team <support@raptorengineering.com>
Thu, 14 Apr 2022 00:56:47 +0000 (19:56 -0500)
commit53351b860f660d645c0d8ec32dff8e4adc6a866a
tree8af41dc12c1815a0f8126ba43e5947106857fc0c
parent2fc4acde28074b5c3bf8607fdf7d923e017df260
Add separate memory clock register to SYSCON
src/soc/bus/syscon.py