double the number of lines in the L1 D/I-Cache to match microwatt

early tests halved the number of lines so as to reduce the size of SRAMs
but the issue is that this is mis-matched against the microwatt.dts
device-tree file

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 6d2d3cf2ae425a243722f4ce882fc1935a11807f..a828e3c3c2137b05e3197ef54e2c69bc2a80496e 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -68,7 +68,7 @@ from nmutil.util import wrap
 
 # TODO: make these parameters of DCache at some point
 LINE_SIZE = 64    # Line size in bytes
-NUM_LINES = 16    # Number of lines in a set
+NUM_LINES = 32    # Number of lines in a set
 NUM_WAYS = 4      # Number of ways
 TLB_SET_SIZE = 64 # L1 DTLB entries per set
 TLB_NUM_WAYS = 2  # L1 DTLB number of sets

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 5417c8b365f7ea0bf3c3baf35f6c73cba9936cd7..8010bf2eab37718fd4b1c9533434dccad2d317bb 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -72,7 +72,7 @@ LINE_SIZE      = 64
 # ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
 ROW_SIZE       = WB_DATA_BITS // 8
 # Number of lines in a set
-NUM_LINES      = 16
+NUM_LINES      = 32
 # Number of ways
 NUM_WAYS       = 4
 # L1 ITLB number of entries (direct mapped)