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Revert "store cur_state.pc+4 in separate register to help reduce"
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 12 Mar 2022 14:13:15 +0000
(14:13 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 12 Mar 2022 14:13:15 +0000
(14:13 +0000)
This reverts commit
d9b58d594ede33db2b0290d7edf8e062f5e91460
.
src/soc/simple/issuer.py
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diff --git
a/src/soc/simple/issuer.py
b/src/soc/simple/issuer.py
index 4a3eb4021454fa1020423e5f5fca06c87f867701..cfad831a3fa76a92c71464fbd95dc0554b8328d0 100644
(file)
--- a/
src/soc/simple/issuer.py
+++ b/
src/soc/simple/issuer.py
@@
-815,10
+815,6
@@
class TestIssuerInternal(TestIssuerBase):
fetch_failed = Const(0, 1)
flush_needed = False
fetch_failed = Const(0, 1)
flush_needed = False
- # create a register with pc+4 as a way to reduce combinatorial chains
- pc4 = Signal.like(cur_state.pc)
- sync += pc4.eq(cur_state.pc + 4)
-
# set priv / virt mode on I-Cache, sigh
if isinstance(self.imem, ICache):
comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR])
# set priv / virt mode on I-Cache, sigh
if isinstance(self.imem, ICache):
comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR])
@@
-902,7
+898,7
@@
class TestIssuerInternal(TestIssuerBase):
m.next = "INSN_READY"
with m.Else():
# fetch the rest of the instruction from memory
m.next = "INSN_READY"
with m.Else():
# fetch the rest of the instruction from memory
- comb += self.imem.a_pc_i.eq(
pc
4)
+ comb += self.imem.a_pc_i.eq(
cur_state.pc +
4)
comb += self.imem.a_i_valid.eq(1)
comb += self.imem.f_i_valid.eq(1)
m.next = "INSN_READ2"
comb += self.imem.a_i_valid.eq(1)
comb += self.imem.f_i_valid.eq(1)
m.next = "INSN_READ2"
@@
-929,7
+925,7
@@
class TestIssuerInternal(TestIssuerBase):
# blech, icache returns actual instruction
insn = self.imem.f_instr_o
else:
# blech, icache returns actual instruction
insn = self.imem.f_instr_o
else:
- insn = get_insn(self.imem.f_instr_o,
pc
4)
+ insn = get_insn(self.imem.f_instr_o,
cur_state.pc+
4)
sync += dec_opcode_i.eq(insn)
m.next = "INSN_READY"
# TODO: probably can start looking at pdecode2.rm_dec
sync += dec_opcode_i.eq(insn)
m.next = "INSN_READY"
# TODO: probably can start looking at pdecode2.rm_dec