make check of LDSTMode.update conditional in PowerDecoder2

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 5df3f16c7c4d82e83cacea65b17d86b47814e046..e24de8a30e2d2f766828b5b535a64bbeba442548 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -369,10 +369,11 @@ class DecodeOut2(Elaboratable):
         m = Module()
         comb = m.d.comb
 
-        # update mode LD/ST uses read-reg A also as an output
-        with m.If(self.dec.op.upd == LDSTMode.update):
-            comb += self.reg_out.eq(self.dec.RA)
-            comb += self.reg_out.ok.eq(1)
+        if hasattr(self.dec.op, "upd"):
+            # update mode LD/ST uses read-reg A also as an output
+            with m.If(self.dec.op.upd == LDSTMode.update):
+                comb += self.reg_out.eq(self.dec.RA)
+                comb += self.reg_out.ok.eq(1)
 
         # B, BC or BCREG: potential implicit register (LR) output
         # these give bl, bcl, bclrl, etc.