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remove ld_stbs_done from dcache: not needed
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 8 Mar 2022 15:46:15 +0000
(15:46 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 8 Mar 2022 15:46:35 +0000
(15:46 +0000)
src/soc/experiment/dcache.py
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diff --git
a/src/soc/experiment/dcache.py
b/src/soc/experiment/dcache.py
index 9e75cc01eb59ee42c71ffafdbcec5795c5ff12cb..917e9818999538375ac3ef0e88b4b911687f69c1 100644
(file)
--- a/
src/soc/experiment/dcache.py
+++ b/
src/soc/experiment/dcache.py
@@
-1589,20
+1589,14
@@
class DCache(Elaboratable, DCacheConfig):
pass
with m.Case(State.RELOAD_WAIT_ACK):
pass
with m.Case(State.RELOAD_WAIT_ACK):
- ld_stbs_done = Signal()
- # Requests are all sent if stb is 0
- comb += ld_stbs_done.eq(~r1.wb.stb)
# If we are still sending requests, was one accepted?
with m.If((~bus.stall) & r1.wb.stb):
# If we are still sending requests, was one accepted?
with m.If((~bus.stall) & r1.wb.stb):
- # That was the last word? We are done sending.
- # Clear stb and set ld_stbs_done so we can handle an
- # eventual last ack on the same cycle.
+ # That was the last word? We are done sending. Clear stb
# sigh - reconstruct wb adr with 3 extra 0s at front
wb_adr = Cat(Const(0, self.ROW_OFF_BITS), r1.wb.adr)
with m.If(self.is_last_row_addr(wb_adr, r1.end_row_ix)):
sync += r1.wb.stb.eq(0)
# sigh - reconstruct wb adr with 3 extra 0s at front
wb_adr = Cat(Const(0, self.ROW_OFF_BITS), r1.wb.adr)
with m.If(self.is_last_row_addr(wb_adr, r1.end_row_ix)):
sync += r1.wb.stb.eq(0)
- comb += ld_stbs_done.eq(1)
# Calculate the next row address in the current cache line
rlen = self.LINE_OFF_BITS-self.ROW_OFF_BITS
# Calculate the next row address in the current cache line
rlen = self.LINE_OFF_BITS-self.ROW_OFF_BITS
@@
-1641,7
+1635,7
@@
class DCache(Elaboratable, DCacheConfig):
sync += r1.use_forward1.eq(1)
# Check for completion
sync += r1.use_forward1.eq(1)
# Check for completion
- with m.If(l
d_stbs_done & l
astrow):
+ with m.If(lastrow):
# Complete wishbone cycle
sync += r1.wb.cyc.eq(0)
# Complete wishbone cycle
sync += r1.wb.cyc.eq(0)