fix test run errors

diff --git a/src/TLB/ariane/test/test_plru.py b/src/TLB/ariane/test/test_plru.py
index 9b040e1da5136d153d0a8d97fc4b5bbea42f9c2b..b249f549f47d81226b6d3369117cf763d57ba45a 100644 (file)
--- a/src/TLB/ariane/test/test_plru.py
+++ b/src/TLB/ariane/test/test_plru.py
@@ -6,10 +6,10 @@ from plru import PLRU
 
 from nmigen.compat.sim import run_simulation
 
-def testbench(dut):
+def tbench(dut):
     yield
 
 if __name__ == "__main__":
     dut = PLRU(4)
-    run_simulation(dut, testbench(dut), vcd_name="test_plru.vcd")
-    print("PLRU Unit Test Success")
\ No newline at end of file
+    run_simulation(dut, tbench(dut), vcd_name="test_plru.vcd")
+    print("PLRU Unit Test Success")

diff --git a/src/TLB/ariane/test/test_ptw.py b/src/TLB/ariane/test/test_ptw.py
index e9c5324c0f44f4186e0743c74effd0a82ad497cf..3164501d877e395c607f67e3ddaa90afa19449bc 100644 (file)
--- a/src/TLB/ariane/test/test_ptw.py
+++ b/src/TLB/ariane/test/test_ptw.py
@@ -4,7 +4,7 @@ sys.path.append("../../../TestUtil")
 
 from nmigen.compat.sim import run_simulation
 
-from ptw import PTW, PTE
+from TLB.ariane.ptw import PTW, PTE
 
 
 def testbench(dut):

diff --git a/src/TLB/ariane/test/test_tlb.py b/src/TLB/ariane/test/test_tlb.py
index aab1d43ca09ec6ecf8b20912bcd591a8db1f4015..ef52ba742946282c803cc6f3dc11248dc621e3b6 100644 (file)
--- a/src/TLB/ariane/test/test_tlb.py
+++ b/src/TLB/ariane/test/test_tlb.py
@@ -4,7 +4,7 @@ sys.path.append("../../../TestUtil")
 
 from nmigen.compat.sim import run_simulation
 
-from tlb import TLB
+from TLB.ariane.tlb import TLB
 
 def set_vaddr(addr):
     yield dut.lu_vaddr_i.eq(addr)