Fix width of the "extra" input on the Extra decoder

The Extra field is nine bits long.

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index a1a69c995c88cf2e41f6e56280313e4874025bb6..9058b80f514188752b1dfd613eaaac7e805086b1 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -87,7 +87,7 @@ class SVP64ExtraSpec(Elaboratable):
     see https://libre-soc.org/openpower/sv/svp64/
     """
     def __init__(self):
-        self.extra   = Signal(10, reset_less=True)
+        self.extra   = Signal(9, reset_less=True)
         self.etype   = Signal(SVEtype, reset_less=True) # 2 or 3 bits
         self.idx     = Signal(SVEXTRA, reset_less=True) # which part of extra
         self.spec  = Signal(3) # EXTRA spec for the register