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authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 7 Jan 2022 16:59:59 +0000 (16:59 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 7 Jan 2022 16:59:59 +0000 (16:59 +0000)
src/soc/experiment/test/test_loadstore1.py

index 7d258a4e72921077a2b02b2e1c1f23c4f9b05df8..b418b8841feef5978821a24136f8ad3def8e5bb6 100644 (file)
@@ -219,6 +219,7 @@ def mmu_lookup(dut,addr):
     yield
     yield
 
+
 def _test_loadstore1_ifetch_multi(dut, mem):
     mmu = dut.submodules.mmu
     ldst = dut.submodules.ldst
@@ -879,6 +880,7 @@ def test_loadstore1_invalid():
     with sim.write_vcd('test_loadstore1_invalid.vcd'):
         sim.run()
 
+
 def test_loadstore1_ifetch_invalid():
     m, cmpi = setup_mmu()
 
@@ -900,6 +902,7 @@ def test_loadstore1_ifetch_invalid():
                       traces=[m.debug_status]): # include extra debug
         sim.run()
 
+
 def test_loadstore1_ifetch_multi():
     m, cmpi = setup_mmu()
     wbget.stop = False