get first revision setvl operational in ISACaller

diff --git a/libreriscv b/libreriscv
index f9d7203c317b4f06900af38ad065d66ae328ce28..923961d3c598d9eeeaae184e50a448404f4b1d8f 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit f9d7203c317b4f06900af38ad065d66ae328ce28
+Subproject commit 923961d3c598d9eeeaae184e50a448404f4b1d8f

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index d103183a5621a58afdeaaa0796491841529e4353..689f656b5ba095d6c87495761fce3e2efab1dfd2 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -62,6 +62,7 @@ REG_SORT_ORDER = {
     "CA": 0,
     "CA32": 0,
     "MSR": 0,
+    "SVSTATE": 0,
 
     "overflow": 1,
 }
@@ -334,12 +335,14 @@ def get_pdecode_idx_out(dec2, name):
     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
     out = yield dec2.e.write_reg.data
     o_isvec = yield dec2.o_isvec
-    print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
     # identify which regnames map to out / o2
     if name == 'RA':
+        print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
         if out_sel == OutSel.RA.value:
             return out, o_isvec
     elif name == 'RT':
+        print ("get_pdecode_idx_out", out_sel, OutSel.RT.value, 
+                                      OutSel.RT_OR_ZERO.value, out, o_isvec)
         if out_sel == OutSel.RT.value:
             return out, o_isvec
     print ("get_pdecode_idx_out not found", name)
@@ -441,7 +444,7 @@ class ISACaller:
                                'memassign': self.memassign,
                                'NIA': self.pc.NIA,
                                'CIA': self.pc.CIA,
-                               'SVSTATE': self.svstate,
+                               'SVSTATE': self.svstate.spr,
                                'CR': self.cr,
                                'MSR': self.msr,
                                'undefined': undefined,
@@ -674,7 +677,7 @@ class ISACaller:
                               pfx.insn[9].value == 0b1)
         self.pc.update_nia(self.is_svp64_mode)
         self.namespace['NIA'] = self.pc.NIA
-        self.namespace['SVSTATE'] = self.svstate
+        self.namespace['SVSTATE'] = self.svstate.spr
         if not self.is_svp64_mode:
             return
 
@@ -818,6 +821,11 @@ class ISACaller:
         if name not in ['mtcrf', 'mtocrf']:
             illegal = name != asmop
 
+        # sigh deal with setvl not being supported by binutils (.long)
+        if asmop.startswith('setvl'):
+            illegal = False
+            name = 'setvl'
+
         if illegal:
             print("illegal", name, asmop)
             self.TRAP(0x700, PIb.ILLEG)
@@ -873,7 +881,7 @@ class ISACaller:
             # in case getting the register number is needed, _RA, _RB
             regname = "_" + name
             self.namespace[regname] = regnum
-            print('reading reg %s %d' % (name, regnum), is_vec)
+            print('reading reg %s %s' % (name, str(regnum)), is_vec)
             reg_val = self.gpr(regnum)
             inputs.append(reg_val)
 
@@ -1002,7 +1010,7 @@ class ISACaller:
                 self.svstate.srcstep += SelectableInt(1, 7)
                 self.pc.NIA.value = self.pc.CIA.value
                 self.namespace['NIA'] = self.pc.NIA
-                self.namespace['SVSTATE'] = self.svstate
+                self.namespace['SVSTATE'] = self.svstate.spr
                 print("end of sub-pc call", self.namespace['CIA'],
                                      self.namespace['NIA'])
                 return # DO NOT allow PC to update whilst Sub-PC loop running
@@ -1011,11 +1019,11 @@ class ISACaller:
             print ("    svstate.srcstep loop end (PC to update)")
             self.pc.update_nia(self.is_svp64_mode)
             self.namespace['NIA'] = self.pc.NIA
-            self.namespace['SVSTATE'] = self.svstate
+            self.namespace['SVSTATE'] = self.svstate.spr
 
         # UPDATE program counter
         self.pc.update(self.namespace, self.is_svp64_mode)
-        self.svstate = self.namespace['SVSTATE']
+        self.svstate.spr = self.namespace['SVSTATE']
         print("end of call", self.namespace['CIA'],
                              self.namespace['NIA'],
                              self.namespace['SVSTATE'])
@@ -1047,7 +1055,8 @@ def inject():
             result = func(*args, **kwargs)
             print("globals after", func_globals['CIA'], func_globals['NIA'])
             print("args[0]", args[0].namespace['CIA'],
-                  args[0].namespace['NIA'])
+                  args[0].namespace['NIA'],
+                  args[0].namespace['SVSTATE'])
             args[0].namespace = func_globals
             #exec (func.__code__, func_globals)
 

diff --git a/src/soc/decoder/isa/test_caller_setvl.py b/src/soc/decoder/isa/test_caller_setvl.py
index 6833a9253646b898bfdcaa8757e0c8a9a7a31481..5e28bdd055e8be8bcf87696234006b92af4feb59 100644 (file)
--- a/src/soc/decoder/isa/test_caller_setvl.py
+++ b/src/soc/decoder/isa/test_caller_setvl.py
@@ -22,7 +22,7 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
     def test_setvl_1(self):
-        lst = SVP64Asm(["setvl 1, 1, 3, 1, 1",
+        lst = SVP64Asm(["setvl 1, 0, 9, 1, 1",
                         ])
         lst = list(lst)
 
@@ -34,9 +34,9 @@ class DecoderTestCase(FHDLTestCase):
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, svstate=svstate)
-            print(sim.gpr(1))
-            self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
-            self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
+            print ("SVSTATE after", bin(sim.svstate.spr.asint()))
+            print ("        vl", bin(sim.svstate.vl.asint(True)))
+            print ("        mvl", bin(sim.svstate.maxvl.asint(True)))
 
     def run_tst_program(self, prog, initial_regs=None,
                               svstate=None):

diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py
index 37bcddead339a82d17fd4e4d8030daa4b19e8e4a..54b2635cf2890114469ba6baaf1cacfc0be7613b 100644 (file)
--- a/src/soc/decoder/pseudo/parser.py
+++ b/src/soc/decoder/pseudo/parser.py
@@ -662,6 +662,8 @@ class PowerParser:
         """power : atom
                  | atom trailerlist"""
         if len(p) == 2:
+            print("power dump atom notrailer")
+            print(astor.dump_tree(p[1]))
             p[0] = p[1]
         else:
             print("power dump atom")
@@ -671,7 +673,7 @@ class PowerParser:
             p[0] = apply_trailer(p[1], p[2])
             if isinstance(p[1], ast.Name):
                 name = p[1].id
-                if name in ['RA', 'RS', 'RB', 'RC']:
+                if name in ['RA', 'RS', 'RB', 'RC', 'RT']:
                     self.read_regs.add(name)
 
     def p_atom_name(self, p):
@@ -684,7 +686,7 @@ class PowerParser:
         if self.include_ca_in_write:
             if name in ['CA', 'CA32']:
                 self.write_regs.add(name)
-        if name in ['CR', 'LR', 'CTR', 'TAR', 'FPSCR', 'MSR']:
+        if name in ['CR', 'LR', 'CTR', 'TAR', 'FPSCR', 'MSR', 'SVSTATE']:
             self.special_regs.add(name)
             self.write_regs.add(name)  # and add to list to write
         p[0] = ast.Name(id=name, ctx=ast.Load())