add comments for DEC / TB

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 66cc8d970343901f56627c12572ca84fb50f5aac..e07a78e786b169880df751259060dcfb64ae7ce5 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -763,11 +763,11 @@ class PowerDecode2(Elaboratable):
         # check if instruction is privileged
         is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
 
-        # external interrupt?
-        with m.If(ext_irq & msr[MSR.EE]):
+        # external interrupt? only if MSR.EE set
+        with m.If(ext_irq & msr[MSR.EE]): # v3.0B p944 (MSR.EE)
             self.trap(m, TT.EINT, 0x500)
 
-        # decrement counter: TODO 32-bit version (MSR.LPCR)
+        # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
         with m.If(dec_spr[63] & msr[MSR.EE]): # v3.0B 6.5.11 p1076
             self.trap(m, TT.DEC, 0x900)   # v3.0B 6.5 p1065
 

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 745f4a3de8c3b055834f7d0e79005749b617eb24..91db8019545a802241aa27fc490cc206086f3865 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -331,6 +331,8 @@ class TestIssuer(Elaboratable):
         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
         value to DEC, however the regfile has "passthrough" on it so this
         *should* be ok.
+
+        see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
         """
 
         comb, sync = m.d.comb, m.d.sync