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Auto insert instruction fields into the namespace
author
Michael Nolan
<mtnolan2640@gmail.com>
Sun, 5 Apr 2020 23:28:12 +0000
(19:28 -0400)
committer
Michael Nolan
<mtnolan2640@gmail.com>
Mon, 6 Apr 2020 13:00:07 +0000
(09:00 -0400)
src/soc/decoder/isa/caller.py
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diff --git
a/src/soc/decoder/isa/caller.py
b/src/soc/decoder/isa/caller.py
index 2199d731348e0453f744e64c65b9492ceda2e047..39d99d5e4fbe4d6fec12999e48e0514e6835bdfe 100644
(file)
--- a/
src/soc/decoder/isa/caller.py
+++ b/
src/soc/decoder/isa/caller.py
@@
-129,15
+129,17
@@
class ISACaller:
# from spec
# then "yield" fields only from op_fields rather than hard-coded
# list, here.
# from spec
# then "yield" fields only from op_fields rather than hard-coded
# list, here.
- for name in ['SI', 'UI', 'D', 'BD']:
- signal = getattr(self.decoder, name)
- val = yield signal
- self.namespace[name] = SelectableInt(val, bits=signal.width)
+ fields = self.decoder.sigforms[formname]
+ for name in fields._fields:
+ if name not in ["RA", "RB", "RT"]:
+ sig = getattr(fields, name)
+ val = yield sig
+ self.namespace[name] = SelectableInt(val, sig.width)
def call(self, name):
# TODO, asmregs is from the spec, e.g. add RT,RA,RB
# see http://bugs.libre-riscv.org/show_bug.cgi?id=282
def call(self, name):
# TODO, asmregs is from the spec, e.g. add RT,RA,RB
# see http://bugs.libre-riscv.org/show_bug.cgi?id=282
- fn, read_regs, uninit_regs, write_regs, op_fields,
asmregs, form
\
+ fn, read_regs, uninit_regs, write_regs, op_fields,
form, asmregs
\
= self.instrs[name]
yield from self.prep_namespace(form, op_fields)
= self.instrs[name]
yield from self.prep_namespace(form, op_fields)