80 char limit, remove creation of stall from ack/cyc, it has to be

done in the parent because that is what knows the usage

diff --git a/src/soc/bus/wb_async.py b/src/soc/bus/wb_async.py
index 60844e56055ea1e2402ee92fc9aa3754fbe41325..6775427fd300d4e2113122ba3c9e5354332458fc 100644 (file)
--- a/src/soc/bus/wb_async.py
+++ b/src/soc/bus/wb_async.py
@@ -135,16 +135,6 @@ class WBAsyncBridge(Elaboratable):
                             i_wbs_rty_i=slave_rty
                             );
 
-        # Synthesize STALL signal for master port
-        if hasattr(self.master_bus, "stall"):
-            comb += self.master_bus.stall.eq(self.master_bus.cyc & ~self.master_bus.ack)
-
-        # Convert incoming slave STALL signal to a format that the async bridge understands...
-        if hasattr(self.slave_bus, "stall"):
-            comb += slave_ack.eq(self.slave_bus.ack & ~self.slave_bus.stall)
-        else:
-            comb += slave_ack.eq(self.slave_bus.ack)
-
         # Wire unused signals to 0
         comb += slave_err.eq(0)
         comb += slave_rty.eq(0)
@@ -154,13 +144,19 @@ class WBAsyncBridge(Elaboratable):
         return m
 
     def ports(self):
-        return [self.master_bus.adr, self.master_bus.dat_w, self.master_bus.dat_r,
-                        self.master_bus.we, self.master_bus.sel, self.master_bus.stb,
-                        self.master_bus.cyc, self.master_bus.ack, self.master_bus.err,
+        return [self.master_bus.adr, self.master_bus.dat_w,
+                        self.master_bus.dat_r,
+                        self.master_bus.we, self.master_bus.sel,
+                        self.master_bus.stb,
+                        self.master_bus.cyc, self.master_bus.ack,
+                        self.master_bus.err,
                         self.master_bus.rty,
-                        self.slave_bus.adr, self.slave_bus.dat_w, self.slave_bus.dat_r,
-                        self.slave_bus.we, self.slave_bus.sel, self.slave_bus.stb,
-                        self.slave_bus.cyc, self.slave_bus.ack, self.slave_bus.err,
+                        self.slave_bus.adr, self.slave_bus.dat_w,
+                        self.slave_bus.dat_r,
+                        self.slave_bus.we, self.slave_bus.sel,
+                        self.slave_bus.stb,
+                        self.slave_bus.cyc, self.slave_bus.ack,
+                        self.slave_bus.err,
                         self.slave_bus.rty
                        ]
 
@@ -177,4 +173,4 @@ def create_verilog(dut, ports, test_name):
 
 if __name__ == "__main__":
     wbasyncbridge = WBAsyncBridge(name="wbasyncbridge_0", address_width=30, data_width=32, granularity=8)
-    create_ilang(wbasyncbridge, wbasyncbridge.ports(), "wbasyncbridge_0")
\ No newline at end of file
+    create_ilang(wbasyncbridge, wbasyncbridge.ports(), "wbasyncbridge_0")